TCC76 Datasheet, PDF (111/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
Clock Control Register (CKCTRL)
0x80000400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
PDN IDLE
0
TSTCK
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CIF ADC XTIN PLL UBH GCK TCK LCK USB UART EX1 EX2 0 DAI 0
This register controls various sources of clocks fed to each peripheral. If each control bit (Bit [14:0]) is set to 1,
the corresponding clock is disabled and the peripherals using that clock are also disabled. To enable the clock,
clear the control bit to 0.
Bit Name Type Default Description
31:26 Reserved R
0 Reserved
25 PDN
W
0 Power Down Mode Enable. When this bit is written with “1”, all blocks are
disabled. Do not enable this bit when the PLL is enabled and PLLOUT is
selected. This bit is write-only, always read as zero.
24 IDLE
W
0 Idle Mode Enable. When this bit is written with “1”, only the CPU is disabled.
Do not enable this bit when the PLL is enabled and PLLOUT is selected.
This bit is write-only, always read as zero.
23:20 Reserved R
0 Reserved
19:16 TSTCK R/W 0 Test Clock Output Selection (GPIO_B0 with GTSEL_B0 = 1).
Prior to use this field, user must set GPIO_B0 port appropriately. The
GTSEL_B0 should be set to 1, and the GSEL_B0 should be set to 0. Care
must be taken not to use SDRAM in this mode, because the GPIO_B0 pin
is shared with SD_CKE signal.
0x0 ~ 0x8 Set to Low
0x9
PLLOUT
0xA
PLLOUT xor DIVCLK1(either PLLOUT or XIN)
0xB
DIVCLK1 xor TCLK xor GCLK
0xC
CIFCLK xor DCLK xor EX2CLK
0xD
FCLK xor UHCLK xor EX1CLK
0xE
UTCLK xor UDCLK
0xF
LCLK xor ADCLK xor EX1CLK
15 Reserved R
0 Reserved
14 CIF
R/W 1 CIF Clock Control
(0 = Enable, 1 = Disable)
13 ADC
R/W 1 ADC Clock Control
(0 = Enable, 1 = Disable)
12 XTIN
R/W 1 Sub Oscillator Clock Control
(0 = Enable, 1 = Disable)
This bit has no effect if XTTC32 of PWDCTL is “0” (XTIN always enabled).
11 PLL
R/W 1 PLL Control
(0 = Enable, 1 = Disable)
10 UBH
R/W 1 USB Host Clock Control
(0 = Enable, 1 = Disable)
9 GCK
R/W 1 GSIO Clock Control
(0 = Enable, 1 = Disable)
8 TCK
R/W 1 Timer Clock Control
(0 = Enable, 1 = Disable)
7 LCK
R/W 1 LCD Clock Control
(0 = Enable, 1 = Disable)
6 USB
R/W 1 USB Device Clock Control
(0 = Enable, 1 = Disable)
5 UART R/W 1 UART Clock Control
(0 = Enable, 1 = Disable)
4 EX1
R/W 1 EXT1 Clock Control
(0 = Enable, 1 = Disable)
The EX1 clock can be monitored through GPIO_B29, GPIO_B24, GPIO_B5,
GPIO_B4, GPIO_B3, and GPIO_B2 pins. (Refer to Chapter GPIO)
3 EX2
R/W 1 EXT2 (I2C) Clock Control
(0 = Enable, 1 = Disable)
The EX2 clock can be monitored through GPIO_B28, GPIO_A9 and
GPIO_A10 pins. Refer to GPIO chapter for more information. The EX2 clock
is also a source clock for the I2C core module.
2 Reserved R
1 Reserved
1 DAI
R/W 1 DAI Clock Control
(0 = Enable, 1 = Disable)
0 Reserved R
0 Reserved
Preliminary
8-5