TCC76 Datasheet, PDF (132/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
USB CONTROLLER
FNE [1]
0
1
Type
R
IN FIFO Not Empty
Indicates that no packet of data is in IN-FIFO.
Indicates that at least one packet of data is in IN-FIFO.
IRDY [0] Type
IN Packet Ready
1
W After writing a packet of data into the IN-FIFO, set this bit
to 1.
0
R Indicates that the packet has been successfully sent to
host.
An interrupt is generated when the USB clears this bit to
zero, so the CPU can load the next packet. While this bit
is set, the CPU will not be able to write to the FIFO.
If the ISST flag is set, IRDY flag cannot be set to 1.
*) FNE == 0 && IRDY == 0 : Indicates that there is no packet in the FIFO.
FNE == 1 && IRDY == 0 : Indicates that there is 1 packet in the FIFO.
FNE == 1 && IRDY == 1 : Indicates that there are 2 packets in the FIFO.
IN CSR2 Register (INCSR2n)
15 14 13 12 11 10 9 8 7 6 5 4 3
Reserved
ASET ISO MDIN DMA
This register is used to configure IN type endpoints.
0x80000548
210
Reserved
ASET [7]
0
1
Type
R/W
Auto Set
User set IRDY flag manually. (Default)
Whenever the CPU writes MAXP data, IRDY will
automatically be set by USB. If it writes less data than
MAXP, it must set IRDY manually.
ISO [6]
0
1
ISO/BULK Mode Select
Configures endpoint mode as BULK. (Default)
Configures endpoint mode as ISO.
MDIN [5]
0
1
IN/OUT Select
Configures endpoint direction as OUT type.
Configures endpoint direction as IN type. (Default)
DMA [4]
0
1
DMA Enable
DMA Disable. (Default)
DMA Enable.
Preliminary
9-10