TCC76 Datasheet, PDF (71/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CPU
for example, a program loop that constantly selects the same segment, from
replacing data that is required again in a later iteration of the loop. The overhead for
high associativity is the need to store a larger TAG. In the case of the ARM940T, this
is 26 bits per line.
The address bits are assigned as follows:
Bits 31:6
Selects an address tag in CAM
Bits 5:4
Selects one of the four cache segments
Bits 3:2
Selects a word in the cache line.
3.2.8.2 Instruction Cache
The ARM940T has a 4KB Icache comprising four 64-way associative segments of 16
bytes per line per segment. The Icache uses the physical address generated by the
processor core. It employs a policy of allocate on read-miss and is always reloaded one
cache line (four words) at a time, through the external interface.
The Icache is always disabled on reset.
3.2.8.3 Data Cache
The ARM940T has a 4KB Dcache comprising 256 lines of 16 bytes (four words),
arranged as four 64-way associative segments. It employs an allocate on read-miss policy,
and is always reloaded a cache line (four words) at a time through the external interface.
The Dcache supports both Write-back (WB) and Write-through (WT) modes.
The GCd (Gated Cacheable for data) bit and the GBd (Gated Bufferable for data) bit
control the Dcache behavior. For this reason, the protection unit must be enabled before
the Dcache is enabled.
3.2.8.4 The Write Buffer
The ARM940T provides a write buffer to improve system performance. The write buffer
can buffer up to eight words of data and four separate non-sequential addresses.
Write buffer behavior is controlled by the protection region attributes of the region that
store being performed and by the Dcache and control bits (GCd and GBd) from the
protection unit. These control bits are generated as follows:
GCd bit
GBd bit
The GCd bit is generated from the cacheable attribute of the
protection region AND the Dcache enable AND the protection unit
enable.
The GBd bit is generated from the bufferable attribute for the
protection region AND the protection unit enable
All accesses are initially non-cacheable and non-bufferable until the protection unit has
been programmed and enabled. It follows that the write buffer cannot be used while the
protection unit is disabled.
On reset, the buffer is flushed.
Preliminary
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