TCC76 Datasheet, PDF (212/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
I2C CONTROLLER
After the signals are enabled, I2CCLK (the main clock of I2C) must be enabled and configured to the proper
frequency. Refer to section “CLOCK GENERATOR” for I2CCLK (EX2CLK) related descriptions.
For internal synchronization, the APB clock frequency must be faster than the I2CCLK frequency.
f_I2CLK ≤ f_HCLK / 4.0
17.3 Register Description
Name
PRES
CTRL
TXR
CMD
RXR
SR
Address
0x00
0x04
0x08
0x0C
0x10
0x14
Table 17.2 I2C Register Map (Base Address = 0x80000800)
Type Reset
Description
R/W
0xFFFF Clock Prescale register
R/W
0x0000 Control Register
W
0x0000 Transmit Register
W
0x0000 Command Register
R
0x0000 Receive Register
R
0x0000 Status Register
Prescale Register (PRES)
0x80000800
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Clock Prescale data
This register is used to prescale the SCL clock line. Due to the structure of the I2C interface, the core uses a
5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change
the value of the prescale register only when ‘EN’ bit is cleared.
Example :
CLK Input frequency = 8MHz , Desired SCL frequency = 100KHz
Prescale = ( 8MHz / (5*100KHz) ) – 1 = 15
Control Register (CTR)
0x80000804
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
EN IEN MOD
RESERVED
EN [7]
0
1
IEN [6]
0
1
MOD [5]
0
1
I2C Core enable bit
Disabled
Enabled
I2C Core interrupt enable bit
Disabled
Enabled
I2C Data Width
8bit Mode
16bit Mode
Preliminary
17-2