TCC76 Datasheet, PDF (165/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
DMA CONTROLLER
BST[10]
BURST Transfer
0
DMA transfer executed with arbitration.
1
DMA transfer executed with no arbitration. ( burst operation )
Arbitration means that at the end of every HOP transfer, the AHB bus is released from DMA
channel so other master can occupy the bus when that master has requested the bus.
Burst means that once the DMA request occurs, all of transfers are executed without further
DMA requests.
TYPE [9:8]
Transfer Type
00
SINGLE transfer with edge-triggered detection
11
SINGLE transfer with level-sensitive detection
01
HW transfer
10
SW transfer
In SINGLE Type, After one Hop data transferring DMA checks External DMA Request
(DREQ ) and then if its bit is active , DMA transfers next hop data . DREQ is detected level-
sensitive or edge-triggered by SINGLE transfer TYPE.
The 1 Hop of transfer means 1 burst of read followed by 1 burst of write. 1 burst means 1, 2 or 4
consecutive read or write cycles defined by BSIZE field of CHCTRL register. The Figure 13.2
illustrates the relation among the above transfers.
DMA Transfer
1 Hop of Transfer
1 Hop of Transfer
1 Burst of Read
1 Burst of Write
R R R R WWWW
1 Burst of Read
1 Burst of Write
R R R R WWWW
* R : Read cycle for 8,16 or 32bit data
* W : Write cycle for 8,16 or 32bit data
* Arbitration Mode
Figure 13.2 Relation between Hop and Burst Transfers (If burst size is 4.)
Hardware type transfer means that the DMA transfer triggered by external or internal hardware
blocks selected by DMASEL field in CHCTRL register. This field has same mapping with
interrupt enable flag of interrupt controller, so the DMA transfer can be occurred as like as
interrupt is generated.
Software type transfer means that the DMA transfer triggered by EN bit of CHCTRL Register .
When this is set to 1, transfer request signal is generated internally and then the transfer begins
immediately.
Hardware demand type transfer (HW_DEMAND) means that once the DMA request occurs,
DMA checks request signal each hop transfer, and if request signal is set, DMA transfer one
hope’s data. After transferring all hope’s data, DMA operation will be finished.
Figure 13.3 is the example of various types of transfer.
Preliminary
13-5