TCC76 Datasheet, PDF (110/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
8.2 Register Description
Table 8.2 Clock Generator Register Map (Base Address = 0x80000400)
Name
Address Type
Reset Description
CKCTRL
0x00
R/W 0x00007FFE Clock Control Register
PLLMODE
0x04
R/W 0x00002E02 PLL Control Register
SCLKmode
0x08
R/W 0x00082000 System Clock Control Register
DCLKmode
0x0C
R/W 0x00000800 DCLK (DAI/CODEC) Control Register
EACLKmode
0x10
R/W 0x00000000 ADCLK and EX2CLK Control Register
EX1CLKmode
0x14
R/W 0x00000000 EX1CLK Control Register
UTCLKmode
0x18
R/W 0x000001BE UTCLK (UART) Control Register
UBCLKmode
0x1C
R/W 0x00000000 UBCLK (USB) Control Register
LCLKmode
0x20
R/W 0x00000000 LCLK (LCD) Control Register
TCLKmode
0x24
R/W 0x00000000 TCLK (Timer) Control Register
GCLKmode
0x28
R/W 0x00000000 GCLK (GSIO) Control Register
CIFCLKmode
0x2C
R/W 0x00000000 CIFCLK Control Register
SW_nRST
0x3C
R/W 0x0000FEFF Software Reset for each peripherals
PWDCTL
0x40
R/W 0x00000000 Power Down Control
DIVMODE
0x44
R/W 0x00000000 Divider Mode Enable (DCO Disable)
HCLKSTOP
0x48
R/W 0x00000000 HCLK Stop Control
XTIN is selected if PW DCTL[7] (XTTC32) == 0
XIN
!CKCTRL[25]
XTIN
MUX
MUX
PW DCTL[17]
(XTFCLK)
ZCLK
(32-bit Counter Clock)
MUX ^DIVCLK0
DCO/Divider selected if (SCLKmode[5:0] != 0)
MUX
FCLK
DCO /
Divider
!CKCTRL[24]
!PW DCTL[7] |
!CKCTRL[12] &
!CKCTRL[12] &
(!CKCTRL[25] | PLLmode[19])
(!CKCTRL[25] | PLLmode[19])
PLL
PLLOUT
PLLmode[18]
SCLKmode[5:0] (F_PHASE)
MUX
MUX ^DIVCLK1
DCO/Divider selected if (SCLKmode[13:8] != 0)
MUX
HCLK to CPU
!CKCTRL[11] (PLL)
SCLKmode[15] ? PW DCTL[17] :
PW DCTL[16]
DCO /
Divider
!CKCTRL[24] |
SCLKmode[14]
SCLKmode[13:8] (H_PHASE)
HCLKSTOP[14:0]
Gated
HCLK to
each
peripheral
Divider ^PLLDIVCLK
PW DCTL[9:8] (DVPLL)
MUX
DCLKmode[15:14] (DIVD)
DCO /
Divider
MUX
!CKCTRL[1]
DCLK
DCLKmode[13:0] (D_PHASE)
•
•
•
Figure 8.2 Clock Generator Register Signals
Preliminary
8-4