TCC76 Datasheet, PDF (41/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name Shared Signal
IIDE_INTRQ
IIDE_nRESET
IIDE_nCS3
IIDE_nCS1
IIDE_nUSB
U_CF
U_nRESET
U_nEA
U_nTEST
TEST_MWP
TEST_AG
TEST_SP
TESTEASL
TESTHOE
TESTHWE
TESTREG
TESTPACK
TESTIS16
TESTIO7
TESTIO6
TESTIO5
TESTIO4
TESTCE4
TESTCE3
TESTCE2
TESTFAL
TESTFCL
TESTFRD
TESTFWE
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO_USB
VDD_NOR
VDD_OSC
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDA_ADC
VDDA_PLL
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSS_NOR
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
Ball
A3
B8
P5
P1
J14
G15
C11
H14
C12
N8
C4
A4
C9
N7
R4
J10
A8
A9
J3
J2
J1
K1
K13
M8
L8
L14
K15
M15
L15
F1
L5
J12
D8
P14
A2
K14
F5
H3
N5
G10
E8
D6
G11
H12
D4
L4
N6
L12
D13
E9
F3
K5
L9
F12
F8
F6
Type Description – TCC767
O
Active high Interrupt Request. This pin should be
connected to one of EXINT[3:0]/GPIO_A[15:12] pins.
I Active low hardware reset.
I
Chip Select 3 for the internal IDE interface. This signal
should be connected to one of nCS[2:0]/GPIO_B[4:2].
I
Chip Select 1 for the internal IDE interface. This signal
should be connected to one of nCS[2:0]/GPIO_B[4:2].
I
IDE / USB Mode Selection signal.
1: IDE Mode, 0: USB Mode.
I
Internal IDE Mode Select Signal. For normal operation,
connect this signal to IIDE_nUSB described above.
I Reset Signal
I EAMODE Select for Test. Pull-up for normal operation.
I Test Mode. (active low). Pull-up for normal operation.
I Reserved for Chip Test. Pull-up for normal operation.
I Reserved for Chip Test. Pull-down for normal operation.
I/O Reserved for Chip Test. Pull-down for normal operation.
I Reserved for Chip Test. Pull-down for normal operation.
I/O Reserved for Chip Test. Pull-down for normal operation.
I/O R eserved for Chip Test. Pull-up for normal operation.
I/O R eserved for Chip Test. Pull-up for normal operation.
I/O Reserved for Chip Test.
I/O Reserved for Chip Test.
I/O Reserved for Chip Test.
I/O Reserved for Chip Test.
I/O Reserved for Chip Test.
I/O Reserved for Chip Test.
I/O Reserved for Chip Test.
I/O Reserved for Chip Test.
I/O Reserved for Chip Test.
O Reserved for Chip Test.
O Reserved for Chip Test.
O Reserved for Chip Test.
O Reserved for Chip Test.
Power Pins
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Digital Power for I/O (3.3V)
Digital Power for I/O (3.3V)
Digital Power for I/O (3.3V)
Digital Power for I/O (3.3V)
Power for USB I/O (3.3V)
Digital Power for NOR Flash (3.3V)
Digital Power for Oscillators (1.8V)
Digital Power for Internal Core (1.8V)
Digital Power for Internal Core (1.8V)
Digital Power for Internal Core (1.8V)
Digital Power for Internal Core (1.8V)
Digital Power for Internal Core (1.8V)
Digital Power for Internal Core (1.8V)
Analog Power for ADC (3.3V)
Analog & Digital Power for PLL (1.8V)
Digital Ground for I/O
Digital Ground for I/O
Digital Ground for I/O
Digital Ground for I/O
Digital Ground for I/O
Digital Ground for NOR Flash
Digital Ground for Internal
Digital Ground for Internal
Digital Ground for Internal
Digital Ground for Internal
Digital Ground for Internal
Digital Ground for Internal
Preliminary
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