TCC76 Datasheet, PDF (39/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name Shared Signal
GPIO_B[21] / BM[0] BCLK
GPIO_B[9]
GPIO_B[8]
GPIO_B[7]
GPIO_B[5]
GPIO_B[4]
GPIO_B[3]
GPIO_B[2]
GPIO_B[1]
GPIO_B[0]
GPIO_D[17]
GPIO_D[16]
GPIO_D[15]
ADIN0
ADIN2
ADIN4
UT_RX
UT_TX / SD_nCS
nCS[3]
nCS[2]
nCS[1]
nCS[0]
SD_nCS / SD_nCLK
SD_CKE
FGPIO[10] / SCL
FGPIO[9] / SDA
FGPIO[8]
XIN
XOUT
XFILT
XTIN
XTOUT
XSCI
XSCO
TDI
TMS
TCK
TDO
nTRST
MODE1
PKG
nRESET
DMRS
DPRS
DM
DP
RREF
RPU
MS_CLK
MS_BS
MS_D[3]
MS_D[2]
Ball
M11
L10
L11
N11
M7
R2
M3
N1
P2
M10
E12
C14
B15
F14
G13
E15
K12
K11
G14
L13
M14
C2
B2
D11
C10
B11
A12
D10
C13
F11
J11
E2
F4
C3
C1
B4
D1
L2
M2
M1
L3
Type Description – TCC767
GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK.
The status of BM[2:0] is latched at the rising edge of nRESET and
I/O used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
I/O GPIO_B[9 ] / UART RX Signal
I/O GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select
I/O GPIO_B[7]
I/O GPIO_B[5] / External Chip Select 3
I/O GPIO_B[4] / External Chip Select 2
I/O GPIO_B[3] / External Chip Select 1
I/O GPIO_B[2] / External Chip Select 0
I/O
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
SDRAM.
I/O GPIO_B[0] / SDRAM clock control
I/O GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
I/O GPIO_D[16] / Fast GPIO bit 9 / I2C SDA
I/O GPIO_D[15] / Fast GPIO bit 8
ADC Input Pins
AI General purpose multi-channel ADC input 0
AI General purpose multi-channel ADC input 2
AI General purpose multi-channel ADC input 4
Clock Pins
I
Main Crystal Oscillator Input for PLL. Input voltage must
not exceed VDD_OSC (1.95V max).
O Main Crystal Oscillator Output for PLL
AO PLL filter output
I
Sub Crystal Oscillator Input. 32.768kHz is recommended.
Input voltage must not exceed VDD_OSC (1.95V max).
O Sub Crystal Oscillator Output
I Crystal Oscillator Input for USB 2.0
O Crystal Oscillator Output for USB 2.0
JTAG Interface Pins
I JTAG serial data input for ARM940T
I JTAG test mode select for ARM940T
I JTAG test clock for ARM940T
I/O JTAG serial data output for ARM940T. External pull-up resistor
is required to prevent floating during normal operation.
I JTAG reset signal for ARM940T. Active low.
Mode Control Pins
I
Mode Setting Input 1. Used for programming internal NOR
flash. Pull-down for normal operation.
I Package ID. Pull-up for normal operation.
I System Reset. Active low.
USB 2.0 Interface Pins
I/O
USB 1.1 D- signal.
Connect to external series resistor (39Ω±1%).
I/O
USB 1.1 D+ signal.
Connect to external series resistor (39Ω±1%).
I/O USB 2.0 D- signal.
I/O USB 2.0 D+ signal.
I
Connect external reference resistor (12.1kΩ±1%) to
ground (VSS_U20).
I
Connect external pull-up resistor(1.5kΩ±1%) to USB 2.0
analog power (VDDA_U20).
MS & MSPRO Interface Pins
O MS/MSPRO Serial protocol Clock signal.
I/O MS/MSPRO Serial protocol Bus State signal.
I/O MS/MSPRO Data Line [3]
I/O MS/MSPRO Data Line [2]
Preliminary
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