TCC76 Datasheet, PDF (43/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
1.4.6 TCC768 Pin Description
Signal Name
SD_CKE
SD_CLK
SD_nCS
XA[21]
XA[20]
XA[19]
XA[18]
XA[17]
XA[16]
XA[15]
XA[14]
XA[13]
XA[12]
XA[11]
XA[10]
XA[9]
XA[8]
XA[7]
XA[6]
XA[5]
XA[4]
XA[3]
XA[2]
XA[1]
XA[0]
XD[15]
XD[14]
XD[13]
XD[12]
XD[11]
XD[10]
XD[9]
XD[8]
XD[7]
XD[6]
XD[5]
XD[4]
XD[3]
XD[2]
XD[1]
XD[0]
NCS[3]
NCS[2]
NCS[1]
NCS[0]
ND_nWE
nWE
nOE
READY
Shared Signal
GPIO_B[0]
GPO
GPIO_B[1]
DQM[0]
DQM[1]
ND_CLE
SD_nRAS / ND_ALE
SD_nCAS
SD_BA[1]
SD_BA[0]
ND_nOE[3] / GPIO_B[5]
ND_nOE[2] / GPIO_B[4]
ND_nOE[1] / GPIO_B[3]
ND_nOE[0] / GPIO_B[2]
GPIO_B[7]
Table 1.8 TCC768 Pin Description
Ball Type Description – TCC768
External Memory Interface Pins
J8
I/O SDRAM Clock Enable signal. Active high. / GPIO_B[0]
SDRAM Clock / GPO. SD_CLK can be used as a general
L5 I/O purpose output. Refer to section “MEMORY CONTROLLER”.
(MCFG register Bit[3] and Bit[1])
L6 I/O Chip select signal for SDRAM, Active low / GPIO_B[1]
L4
I/O External Bus Address Bit [21] / Data I/O Mask 0
K4 I/O External Bus Address Bit [20] / Data I/O Mask 1
K3 I/O External Bus Address Bit [19]
L2
I/O External Bus Address Bit [18]
L3
I/O External Bus Address Bit [17] / CLE for NAND Flash
External Bus Address Bit [16] / SDRAM RAS signal / ALE for
G3 I/O
NAND Flash
M3 I/O External Bus Address Bit [15] / SDRAM CAS signal
M2 I/O External Bus Address Bit [14] / SDRAM Bank Address 1
M1 I/O External Bus Address Bit [13] / SDRAM Bank Address 0.
J4
I/O External Bus Address Bit [12]
K2 I/O External Bus Address Bit [11]
M4 I/O External Bus Address Bit [10]
J1
I/O External Bus Address Bit [9]
H4 I/O External Bus Address Bit [8]
H5 I/O External Bus Address Bit [7]
H1 I/O External Bus Address Bit [6]
G6 I/O External Bus Address Bit [5]
H2 I/O External Bus Address Bit [4]
G5 I/O External Bus Address Bit [3]
G4 I/O External Bus Address Bit [2]
G7 I/O External Bus Address Bit [1]
G8 I/O External Bus Address Bit [0]
A3 I/O External Bus Data Bit [15]
F4 I/O External Bus Data Bit [14]
E2 I/O External Bus Data Bit [13]
E5 I/O External Bus Data Bit [12]
D8 I/O External Bus Data Bit [11]
F7 I/O External Bus Data Bit [10]
E1 I/O External Bus Data Bit [9]
F6 I/O External Bus Data Bit [8]
E3 I/O External Bus Data Bit [7]
D4 I/O External Bus Data Bit [6]
C2 I/O External Bus Data Bit [5]
B1 I/O External Bus Data Bit [4]
A7 I/O External Bus Data Bit [3]
B2 I/O External Bus Data Bit [2]
A10 I/O External Bus Data Bit [1]
F8 I/O External Bus Data Bit [0]
H6
I/O
External Bus Chip Select [3] / NAND Flash Output Enable [3] /
GPIO_B[5]. This pin should be connected to FCSN.
J6
I/O
External Bus Chip Select [2] / NAND Flash Output Enable [2] /
GPIO_B[4]
K6
I/O
External Bus Chip Select [1] / NAND Flash Output Enable [1] /
GPIO_B[3]
J5
I/O
External Bus Chip Select [0] / NAND Flash Output Enable [1] /
GPIO_B[2]
L10 I/O NAND flash WE.Active low. / GPIO_B[7]
M5 I/O Static Memory Write Enable signal. Active low.
H7 I/O Static Memory Output Enable signal. Active low.
J11
I Ready information from external device.
Preliminary
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