TCC76 Datasheet, PDF (162/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
DMA CONTROLLER
13.2 Register Description
Table 13.1 DMA Controller Register Map (Base Address = 0x80000E00)
Name
Address Type
Reset
Description
C
ST_SADR0
H
SPARAM0
0x00
R/W
0x04/0x08
R/W
-
Start Address of Source Block
-
Parameter of Source Block
A
C_SADR0
0x0C
R
-
Current Address of Source Block
N
ST_DADR0
N
DPARAM0
E
C_DADR0
L
HCOUNT0
0
CHCTRL0
0x10
0x14/0x18
0x1C
0x20
0x24
R/W
-
Start Address of Destination Block
R/W
-
Parameter of Destination Block
R
-
Current Address of Destination Block
R/W
0x00000000 Initial and Current Hop count
R/W
0x00000000 Channel Control Register
CHCONFIG
0x2C
R/W
-
Channel Configuration Register
C
ST_SADR1
0x30
R/W
-
Start Address of Source Block
H
SPARAM1
0x34/0x38
R/W
-
Parameter of Source Block
A
C_SADR1
0x3C
R
-
Current Address of Source Block
N
ST_DADR1
0x40
R/W
-
Start Address of Destination Block
N
DPARAM1
E
C_DADR1
L
HCOUNT1
1
CHCTRL1
0x44/0x48
0x4C
0x50
0x54
R/W
-
Parameter of Destination Block
R
-
Current Address of Destination Block
R/W
0x00000000 Initial and Current Hop count
R/W
0x00000000 Channel Control Register
Start Source Address Register (ST_SADR)
0x80000E00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST_SADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_SADR[15:0]
This register contains the start address of source memory block for DMA transfer. The transfer
begins reading data from this address.
Start Destination Address Register (ST_DADR)
0x80000E10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST_DADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_DADR[15:0]
This register contains the start address of destination memory block for DMA transfer.
Source Block Parameter Register (SPARAM)
31 30 29 28 27 26 25 24 23 22
SMASK[23:8]
15 14 13 12 11 10 9 8 7 6
SMASK[7:0]
0x80000E04 / 0x80000E08
21 20 19 18 17 16
543210
SINC[7:0]
SMASK [31:8]
Source Address Mask Register
0
non-masked
1
Masked so that source address bit doesn’t be changed during DMA
transfer
Each bit field controls the dedicated bit of source address field. That is, if SMASK[23] is set to 1,
the 28th bit of source address is masked, and if SMASK[22] is set to 1, the 27th bit of source
Preliminary
13-2