TCC76 Datasheet, PDF (88/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTERRUPT CONTROLLER
Trigger Mode Register (TMODE)
0x80000130
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CIF I2C ADC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDY TC32 DMA LCD CDIF UBH GS UB UT TC I2T I2R
Reserved
This register selects trigger mode (0: edge, 1:level) for each internal interrupt source.
Synchronization Control Register (SYNC)
0x80000134
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CIF I2C ADC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDY TC32 DMA LCD CDIF UBH GS UB UT TC I2T I2R
Reserved
By default, all internal interrupt source lines are synchronized to HCLK. This register disables synchronization
registers (0: sync enabled, 1:sync disabled). Do not disable synchronization if an interrupt source is asynchronous to
HCLK
Wakeup Control Register (WKUP)
0x80000138
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CIF I2C ADC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDY TC32 DMA LCD CDIF UBH GS UB UT TC I2T I2R E3 E2 E1 E0
This register enables each interrupt source to be used as an asynchronous wakup event for Power Down or IDLE
mode. By default, all interrupt source lines are used for system wakeup events in power down mode. (0: enabled, 1:
disabled). Appropriate bits must be enabled before the system enters power down mode (clock stop mode).
Otherwise, system cannot wakeup. Refer to section “Power Down Mode” and “IDLE mode” in Chapter “Clock
Generator”.
Before enable E3 ~ E0 (external interrupt pins), FE3 ~ FE0 bits of ICFG register must be changed to control the
polarity of each external interrupt pin. In wakup event control logic, FE3 ~ FE0 bits of ICFG are used as polarity
control bits for the external interrupt pins (“0” indicates active low, “1” indicates active high). Watch out for the different
interpretation of ICFG register between two logics.
FEn, DTYPEn of
ICFG Register
000
001
010
011
100
101
110
111
Table 5.3 ICFG Usage for WakeUp Event
Interrupt Generation Logic
WakeUp Event Control Logic
Triggering
Noise Filter
Falling edge triggered
Filter enabled
Rising edge triggered
Both edge triggered
Filter enabled _{Low level trigger, filter disabled}
Filter enabled
Low level triggered
Filter enabled
Falling edge triggered
Filter disabled
Rising edge triggered
Both edge triggered
Filter disabled _{High level trigger, filter disabled}
Filter disabled
High level triggered
Filter enabled
As long as the HCLK is alive, any interrupt source lines with the corresponding Interrupt Enable bit active can
wakeup the system from Power Down or IDLE Mode. (The TCC76x Clock Generator also accepts nIRQ and
nFIQ for wakeup). But when the HCLK is stopped, the Interrupt Controller is stopped also, and no event output
is generated to the clock generation logic. Thus, the system can never be woke up if Wakup Control Register is
not used at all.
Wakeup Control Register must be used in Power Down or IDLE Mode if the HCLK is to be disabled.
It is recommended to disable Interrupt Enable Register if Wakeup Control Register bits are used.
Preliminary
5-6