TCC76 Datasheet, PDF (202/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
MEMORY CONTROLLER
URDY [19]
Use Ready
Ready / Busy signal monitoring is enabled
1
The memory controller extends access cycle until the state of READY
pin indicates that the access request has accomplished.
*) Refer to Figure 15.3 for ready(busy) cycle extension. Don’t use this feature when access
NAND flash. NAND flash’s READY signal is for waiting from end of command cycle to start of
data cycle so it is not adequate for extension of each cycle.
RDY [18]
Ready / Busy Select
The READY(MODE0) pin indicate the READY signal.
0
The memory controller extends access cycle until this pin goes to high
state.
The READY(MODE0) pin indicate the BUSY signal.
1
The memory controller extends access cycle until this pin goes to low
state.
*) Refer to Figure 15.3 for ready/busy cycle extension.
AMSK [14]
Address Mask Bit
0
Upper half of data bus is masked to zero.
*) In case of 16bit width NAND flash, the upper half byte must be held low, during address
cycles. This bit must be set to zero. But if the system uses multiple NAND flashes by sharing a
chip select but separating each data to 16 or 32bit data bus of the TCC76x, the AMSK must be set
to 1, so the address can be fed to each NAND flashes.
PSIZE [13:12]
Page size of NAND Flash
The size of one page for NAND type flash.
psize
It represents byte per page calculated by the following equation.
1 Page = 256 * 2^psize
*) Refer to Table 15.3 about the relationship between the address generation and each page size
configuration.
CADR [11:9]
Number of Address Cycles
N
The number of address command cycle for NAND type flash.
(N+1) cycle is used for generating address cycle command.
*) Refer to sub-register of NAND type memory for more information of PSIZE and CADR field.
STP [8:6]
N
Number of Cycle for Setup Time (tSH)
N cycle is issued between the falling edge of nCS[n] and nOE / nWE.
PW[7:0]
[29:28,17:15,5:3]
N ( = 0~255 )
Number of Cycle for Pulse Width (tPW)
(N+1) cycle is issued between the falling and rising edge of nOE /
nWE.
HLD [2:0]
N
Number of Cycle for Hold Time (tHLD)
N cycle is issued between the rising edge of nOE / nWE and nCS[n].
The following figure displays the element cycle diagram for external memories.
Preliminary
15-10