TCC76 Datasheet, PDF (17/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
1.4 Pin Description
The status of the following GPIO pins are latched at the rising edge of nRESET and used to determine the system bus width and
boot mode. External devices must not drive output levels onto these pins during reset period.
Pin Name
State during reset
State after reset
During normal function with DAI enabled
GPIO_A[9] / BW[1]
Bus Width Configuration Input Normal GPIO Input Mode
GPIO_A[8] / BW[0]
GPIO Output Mode for 2-Wire Interface Clock and Data
GPIO_B[24] / BM[2]
DAO (I2S Digital Audio Output)
GPIO_B[22] / BM[1] Boot Mode Configuration Input Normal GPIO Input Mode
LRCK (I2S Word Clock Output)
GPIO_B[21] / BM[0]
BCLK (I2S Bit Clock Output)
Refer to sections “BOOTING PROCEDURE” and “MEMORY CONTROLLER” for detailed description of BW[1:0] and BM[2:0].
In case of the TCC763, TCC764, TCC766 and TCC768, GPIO_B[22:21]/BM[1:0] signals are connected to internal
audio CODEC pins which have on-chip pull-down resistor. If external pull-up resistors are required for these pins,
4.7kΩ is recommended.
The TCC76x is a CMOS device. Floating level on input signals cause unstable device operation and abnormal
current consumption. Pull-up or pull-down resistors should be used appropriately for input or bidirectional pins.
Notation
I:
O:
I/O:
AI:
AO:
PWR:
GND:
Input
Output
Bidirectional
Analog Input
Analog Output
Power
Ground
1.4.1 TCC760 Pin Description
Signal Name Shared Signal
SD_CKE
SD_CLK
GPIO_B[0]
GPO
SD_nCS
XA[21:20]
XA[19:18]
XA[17]
XA[16]
XA[15]
XA[14]
XA[13]
XA[12:7]
XA[6:0]
XD[15:9]
XD[8:4]
SD_nCLK / GPIO_B[1]
DQM[0:1]
DQS[1:0]
ND_CLE
SD_nRAS / ND_ALE
SD_nCAS
SD_BA[1]
SD_BA[0]
Pin #
56
44
46
43:42
40:39
38
37
36
35
34
31:26
23:17
15:9
6:2
Table 1.2 TCC760 Pin Description
Type Description – TCC760
External Memory Interface Pins
I/O SDRAM Clock Enable signal. Active high. / GPIO_B[0]
SDRAM Clock / GPO. SD_CLK can be used as a general
I/O purpose output. Refer to section “MEMORY CONTROLLER”.
(MCFG register Bit[3] and Bit[1])
Chip select signal for SDRAM, Active low / Inverted SD_CLK for
I/O
DDR SDRAM / GPIO_B[1]
I/O External Bus Address Bit [21:20] / Data I/O Mask 0, 1
I/O External Bus Address Bit [19:18] / DDR SDRAM Data Strobe [1:0]
I/O External Bus Address Bit [17] / CLE for NAND Flash
External Bus Address Bit [16] / SDRAM RAS signal / ALE
I/O
for NAND Flash
I/O External Bus Address Bit [15] / SDRAM CAS signal
I/O External Bus Address Bit [14] / SDRAM Bank Address 1
I/O External Bus Address Bit [13] / SDRAM Bank Address 0.
I/O External Bus Address Bits [12:0]
I/O External Bus Data Bit [15:0]
Preliminary
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