TCC76 Datasheet, PDF (32/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name Shared Signal
GPIO_A[8] / BW[0] SDIN
GPIO_A[7]
GPIO_A[6]
GPIO_A[5]
GPIO_A[4]
GPIO_A[3]
GPIO_A[2]
GPIO_A[1]
GPIO_A[0]
GPIO_B[29]
GPIO_B[28]
GPIO_B[27]
GPIO_B[26]
GPIO_B[25]
SDI1 / FGPIO[7]
TESTRST
TESTUSB
SDO1 / FGPIO[4]
SDI0 / CDAI / FGPIO[3]
FRM0 / CLRCK / FGPIO[2]
SCK0 / CBCLK / FGPIO[1]
SDO0 / FGPIO[0]
USBH_DN
USBH_DP
USB_DN
USB_DP
DAI
GPIO_B[24] / BM[2] DAO
GPIO_B[23]
MCLK
GPIO_B[22] / BM[1] LRCK
GPIO_B[21] / BM[0] BCLK
GPIO_B[9]
GPIO_B[8]
GPIO_B[7]
GPIO_B[5]
GPIO_B[4]
GPIO_B[3]
GPIO_B[2]
GPIO_B[1]
GPIO_B[0]
GPIO_D[17]
UT_RX
UT_TX / SD_nCS
nCS[3]
nCS[2] / TESTCS2
nCS[1]
nCS[0] / TESTCS0
SD_nCS / SD_nCLK
SD_CKE
FGPIO[10] / SCL
Ball
E7
B7
A7
F9
B10
D9
E10
E11
M4
N10
R10
T8
P9
M13
M14
N6
L14
N12
N11
M11
L10
M9
R7
R8
P6
M8
L9
B16
Type Description – TCC766
GPIO_A[8] / Bus Width bit 0. The status of BW[1:0] is latched at the
I/O
rising edge of nRESET and used to determine external bus width.
Refer to section “MEMORY CONTROLLER” for BW[1:0]
description.
I/O GPIO_A[7] / GSIO1 Data In / Fast GPIO bit 7
I/O
GPIO_A[6] / Reset for the internal USB2.0 module. Pull-down for
normal operation.
I/O
GPIO_A[5] / Mode Selection for the internal USB2.0 module. Pull-
up for normal operation.
I/O GPIO_A[4] / GSIO1 Data Output / Fast GPIO bit 4
I/O
GPIO_A[3] / GSIO0 Data In / CD Interface Data / Fast GPIO bit 3.
This pin has an internal pull-up resistor.
I/O
GPIO_A[2] / GSIO0 FRM / CD Interface LRCK / Fast GPIO bit 2
This pin has an internal pull-up resistor.
I/O
GPIO_A[1] / GSIO0 Clock / CD Interface BCLK / Fast GPIO bit 1
This pin has an internal pull-up resistor.
I/O
GPIO_A[0] / GSIO0 Data Out / FGPIO[0]
This pin has an internal pull-up resistor.
I/O GPIO_B[29] / USBH_DN
I/O GPIO_B[28] / USBH_DP
I/O GPIO_B[27] / USB_DN
I/O GPIO_B[26] / USB_DP
I/O
GPIO_B[25] / I2S Interface Data In. Should be connected
externally to ADCDAT pin.
GPIO_B[24] / Boot Mode bit 2 / I2S Interface Data Out.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
I/O “BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
Refer to “Functional Block Diagram” for more information
about internal connectivity.
GPIO_B[23] / I2S Interface Master Clock.
I/O Refer to “Functional Block Diagram” for more information
about internal connectivity.
GPIO_B[22] / Boot Mode bit 1 / I2S Interface LRCK.
The status of BM[2:0] is latched at the rising edge of nRESET and
I/O
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
Internal pull-down resistor is active at power up.
GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK.
The status of BM[2:0] is latched at the rising edge of nRESET and
I/O
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
Internal pull-down resistor is active at power up.
I/O GPIO_B[9 ] / UART RX Signal
I/O GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select
I/O GPIO_B[7]
I/O
GPIO_B[5] / External Chip Select 3. Should be
connected externally to FCSN.
GPIO_B[4] / External Chip Select 2. This pin has an
I/O internal connection to the USB2.0 module. Do not connect
to external components.
I/O GPIO_B[3] / External Chip Select 1
GPIO_B[2] / External Chip Select 0. This pin has an
I/O internal connection to the USB2.0 module. Do not connect
external components.
I/O
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
SDRAM.
I/O GPIO_B[0] / SDRAM clock control
I/O GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
Preliminary
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