TCC76 Datasheet, PDF (57/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
ADDRESS & REGISTER MAP
2.2 Register Map
Name
DADI_L0
DADI_R0
DADI_L1
DADI_R1
DADI_L2
DADI_R2
DADI_L3
DADI_R3
DADO_L0
DADO_R0
DADO_L1
DADO_R1
DADO_L2
DADO_R2
DADO_L3
DADO_R3
DAMR
DAVC
CDDI_0
CDDI_1
CDDI_2
CDDI_3
CICR
Table 2.3 DAI & CDIF Register Map (Base = 0x80000000)
Address Type Reset Description
0x00
R
-
Digital Audio Left Input Register 0
0x04
R
-
Digital Audio Right Input Register 0
0x08
R
-
Digital Audio Left Input Register 1
0x0C
R
-
Digital Audio Right Input Register 1
0x10
R
-
Digital Audio Right Input Register 2
0x14
R
-
Digital Audio Right Input Register 2
0x18
R
-
Digital Audio Right Input Register 3
0x1C
R
-
Digital Audio Right Input Register 3
0x20
R/W
-
Digital Audio Left Output Register 0
0x24
R/W
-
Digital Audio Right Output Register 0
0x28
R/W
-
Digital Audio Left Output Register 1
0x2C
R/W
-
Digital Audio Right Output Register 1
0x30
R/W
-
Digital Audio Left Output Register 2
0x34
R/W
-
Digital Audio Right Output Register 2
0x38
R/W
-
Digital Audio Left Output Register 3
0x3C
R/W
-
Digital Audio Right Output Register 3
0x40
R/W
0x0000 Digital Audio Mode Register
0x44
R/W
0x0000 Digital Audio Volume Control Register
0x80
R
-
CD Digital Audio Input Register 0
0x84
R
-
CD Digital Audio Input Register 1
0x88
R
-
CD Digital Audio Input Register 2
0x8C
R
-
CD Digital Audio Input Register 3
0x90
R/W
0x0000 CD Interface Control Register
Name
IEN
CREQ
IREQ
IRQSEL
ICFG
MREQ
TSTREQ
IRQ
FIQ
MIRQ
MFIQ
TMODE
SYNC
WKUP
Table 2.4 Interrupt Controller Register Map (Base = 0x80000100)
Address Type Reset Description
0x00
R/W
0x0000 Interrupt Enable Register
0x04
W
-
Clear Interrupt Request Register
0x08
R
0x0000 Interrupt Request Flag Register
0x0C
R/W
0x0000 IRQ/FIQ Select Register
0x10
R/W
0x0000 External interrupt configuration register
0x14
R
0x0000 Masked interrupt request flag register
0x18
R/W
0x0000 Test Mode Register (must be remained zero)
0x20
R
-
IRQ Raw Status (IREQ & IRQSEL)
0x24
R
-
FIQ Raw Status (~IREQ & IRQSEL)
0x28
R
-
Masked IRQ Status (IRQ & IEN)
0x2C
R
-
Masked FIQ Status (FIQ & IEN)
0x30
R/W 0x000007C0 Trigger Mode (0: edge, 1:level)
0x34
R/W 0x00000000 Synchronizer Control
0x38
R/W 0x00000000 Wakeup Control
Preliminary
2-3