TCC76 Datasheet, PDF (19/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name Shared Signal
GPIO_A[0]
SDO0 / FGPIO[0]
GPIO_B[29:28]
USBH_DN, USBH_DP
GPIO_B[27:26]
USB_DN, USB_DP
GPIO_B[25]
DAI
GPIO_B[24] / BM[2] DAO
GPIO_B[23]
MCLK
GPIO_B[22] / BM[1] LRCK
GPIO_B[21] / BM[0] BCLK
GPIO_B[9]
UT_RX
GPIO_B[8]
UT_TX / SD_nCS
GPIO_B[7]
ND_nWE
GPIO_B[5:2]
nCS[3:0]
GPIO_B[1]
SD_nCS / SD_nCLK
GPIO_B[0]
SD_CKE
GPIO_D[21:18]
FGPIO[14:11] / CISD[7:4]
GPIO_D[17]
GPIO_D[16]
GPIO_D[15]
FGPIO[10] / SCL / CISHS
FGPIO[9] / SDA / CISVS
FGPIO[9] / CISCLK
ADIN_0
-
ADIN_2
-
ADIN_4
-
XIN
-
XOUT
-
XFILT
-
XTIN
-
XTOUT
-
MODE1
-
PKG1
-
nRESET
-
TDI
-
TMS
-
TCK
-
TDO
-
nTRST
-
VDDIO
-
Pin #
104
54:53
52:51
68
67
66
63
62
61
60
57
50:47
46
56
96:93
92
91
90
82
83
84
74
75
78
69
70
98
89
72
99
100
101
102
103
112
76
33
16
Type Description – TCC760
GPIO_A[0] / General purpose serial I/O 0 Serial Data Output
I/O
FGPIO[0]
I/O GPIO_B[29:28] / USBH_DN, USBH_DP
I/O GPIO_B[27:26] / USB_DN, USB_DP
GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals.
The status of BM[2:0] is latched at the rising edge of nRESET and
I/O used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
I/O GPIO_B[9 ] / UART RX Signal
I/O GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select
I/O GPIO_B[7] / Write Enable for NAND Flash
I/O GPIO_B[5:2] / External Chip Select 3 ~ 0
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
I/O
SDRAM.
I/O GPIO_B[0] / SDRAM clock control
GPIO_D[21:18] / Fast GPIO bits 14 ~11 / Camera Interface Data
I/O
Inputs 3 ~ 0. Internal pull-up resistors are enabled at reset.
I/O GPIO_D[17] / Fast GPIO bit 10/ I2C SCL / Camera Interface Hsync.
I/O GPIO_D[16] / Fast GPIO bit 9 / I2C SDA / Camera Interface Vsync.
I/O GPIO_D[15] / Fast GPIO bit 8 / Camera Interface Clock
ADC Input Pins
AI General purpose multi-channel ADC input 0
AI General purpose multi-channel ADC input 2
AI General purpose multi-channel ADC input 4
Clock Pins
I Main Crystal Oscillator Input for PLL. 12MHz Crystal
must be used if USB Boot Mode is required. Input
voltage must not exceed VDD_OSC (1.95V max).
O Main Crystal Oscillator Output for PLL
AO PLL filter output
I Sub Crystal Oscillator Input. 32.768kHz is recommended.
Input voltage must not exceed VDD_OSC (1.95V max).
O Sub Crystal Oscillator Output
Mode Control Pins
I Mode Setting Input 1. Pull-down for normal operation.
I Package ID1, Pull-up for normal operation.
I System Reset. Active low.
JTAG Interface Pins
I JTAG serial data input for ARM940T
I JTAG test mode select for ARM940T
I JTAG test clock for ARM940T
I/O JTAG serial data output for ARM940T. External pull-up resistor is
required to prevent floating during normal operation.
I JTAG reset signal for ARM940T. Active low.
Power Pins
PWR Digital Power for I/O (1.8V ~ 3.3V)
Preliminary
1-9