TCC76 Datasheet, PDF (70/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CPU
3.2.8 Caches and Write Buffer
3.2.8.1 Cache Architecture
The ARM940T incorporates a 4KB of instruction cache, a 4KB of data cache, and
an 8-word write buffer. The Icache and Dcache have similar architectures, as
illustrated in the following figure.
WDATA[31:0]
A[31:2]
A[31:6]
Line Index
0
1
2
Address TAG
SEG3
SEG2
SEG1
SEG0
Word 0 Word 1 Word 2 Word 3
CAM
RAM
63
A[3:2]
A[5:4]
RDATA[31:0]
3
2
1
0
SEG3
SEG2
SEG1
SEG0
Figure 3.2 4KB Cache Architecture in ARM940T
Each cache comprises four, fully associative 1KB segments which support single-
cycle reads, and either one or two-cycle writes depending on the sequentiality of the
access.
Each cache segment consists of 64 CAM (Content Addressable Memory) rows
which each select one of 64 RAM four-word long lines. during a cache access, a
segment is selected and the access address is compared with the 64 TAGs in the
CAM. If a match occurs (or a hit), the matched line is enabled and the data can be
accessed. If none of the TAGs match (or a miss), then external memory must be
accessed, unless the access is a buffered write in which case the write buffer is used.
If a read access from a cacheable memory region misses, new data is loaded into one
of the 64 row lines of the selected segment. This is an allocate on read-miss
replacement policy. Selection is performed by a randomly clocked target row
counter.
Critical or frequently-accessed instructions or data can be locked into the cache by
restricting the range of the target counter. Locked lines cannot be replaced and
remain in the cache until they are unlocked or flushed.
The CAM allows 64 address TAGs to be stored for an address that selects a given
segment (64-way associativity). This reduces the chance of an address sequence in,
Preliminary
3-4