TCC76 Datasheet, PDF (206/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
MEMORY CONTROLLER
Table 15.3 Page size of NAND Flash
# of Cycle
PSIZE = 0
Address Generation
PSIZE = 1
PSIZE = 2
PSIZE = 3
1^st
ADR[7:0]
ADR[7:0]
ADR[7:0]
ADR[7:0]
2^nd
ADR[15:8]
ADR[16:9]
ADR[10:8]
ADR[11:8]
3^rd
ADR[23:16]
ADR[24:17]
ADR[18:11]
ADR[19:12]
4^th
ADR[31:24]
ADR[31:25]
ADR[26:19]
ADR[27:20]
5^th
-
-
ADR[31:27]
ADR[31:28]
*) ADR means address value that is written to NDLADR or NDRADR register. The shaded cycles represent row
address cycles. That is, NAND address cycles start from there when NDRADR register is accessed.
Single Address Cycle Register (NDIADR)
0x10000000 * M + 0x0C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
NDIADR
*) When CPU writes to this register, one cycle of address cycle is generated.
Data Register (NDDATA)
0x10000000 * M + 0x10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDDATA3
NDDATA2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDDATA1
NDDATA0
*) NDDATA3~1 may be used as the value of data register, otherwise only NDDATA0 is used as
data register. It is dependant on the bus-width of CSCFGx register of NAND flash.
15.5 Internal Memory
In the TCC76x, there is 64Kbytes of SRAM for general purposes and 4Kbytes of ROM for
system initialization. SRAM area is dedicated to area 3 (0x30000000 ~ 0x3FFFFFFF), and also
accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when there are no devices assigned to area 0.
ROM area is dedicated to area E (0xE0000000 ~ 0xEFFFFFFF), and also accessed by area 0
(0x00000000 ~ 0x0FFFFFFF) when RM flag of MCFG register is cleared to 0.
In case of internal ROM, access cycle can be extended by inserting 1 wait cycle. This wait cycle
is determined by writing any value to ROM area.
When writing to address of which the bit 2 is 1 (such as 0xE0000004, 0xE000000C,
0xE0000014, …) , the wait cycle is to be inserted from the next ROM access cycle. On the other
hand writing to address of which the bit 2 is 0 (such as 0xE0000000, 0xE0000008, 0xE0000010,
…), the wait cycle is to be removed from the next ROM access cycle.
In the TCC76x, zero wait access is guaranteed for the internal ROM and SRAM up to 100MHz
AHB clock. The wait cycle insertion feature was preserved for the TCC72x. There is no need
to enable wait cycle.
Preliminary
15-14