TCC76 Datasheet, PDF (199/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
MEMORY CONTROLLER
SDW [7]
0
1
Type
SDRAM High-Frequency Wait
R/W
No additive wait cycle
Additive wait cycle
SDT [6]
0
1
Type
Type of SDRAM
R/W
Single-Data-Rate SDRAM
Double-Data-Rate SDRAM
JTEN [5]
0
1
Type
JTAG Enable
R/W ^{JTAG port is disabled}
JTAG port is enabled
SDEN [4] Type
SDRAM Controller Enable
0
R/W ^{SDRAM controller is disabled}
1
SDRAM controller is enabled
*) When this bit goes from low to high, SDRAM MRS cycle is generated.
This bit must be cleared before CL bit of SDCFG register is changed.
SDS [3]
0
1
Type
SD_CLK output select
R/W
SDRAM Clock is out from SD_CLK pin
GPO bit is out from SD_CLK pin
SRF [2] Type
Self Refresh Cycle Generation
If SDRAM is in standby mode, the refresh cycle is generated a
0
few times automatically, and SDRAM exits from standby state
R/W
and goes back into idle state.
If SDRAM is not in standby mode, the self-refresh cycle is
1
generated, and the SDRAM enters into standby mode and stay
this mode until this flag goes back to low.
*) Do not set while program is executing in SDRAM. SR bit of SDCFG register has the same
function.. Either one can be used for self-refresh mode control.
It is recommended to use the following example sequence to control self-refresh mode.
To enable self-refresh mode,
1. Manipulate cache coherency if necessary.
2. Set SR bit of SDCFG register
3. Set SDS bit of MCFG register
To exit from self-refresh mode,
1. Clear SDS bit of MCFG register
2. Clear SR bit of SDCFG register
The above sequences must be executed in the non-SDRAM area, like internal SRAM or NOR
flash and while the SDRAM is in self-refresh mode, code should not access the SDRAM area.
GPO [1]
0/1
Type
SD_CLK output
R/W When SDS bit is high, this bit is out through SD_CLK pin
Preliminary
15-7