TCC76 Datasheet, PDF (210/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
ECC (ERROR CORRECTION CODE)
and 16 bits for line parity) as follows:
P1, P1’, P2, P2’, P4, P4’, P8, P8’, P16, P16’, ……, P1024, P1024’
The parity data that have been generated are stored as follows.
SLC_ECCx_0
SLC_ECCx_1
SLC_ECCx_2
Bit7
P64
P1024
P4
Bit6
P64’
P1024’
P4’
Bit5
P32
P512
P2
Bit4
P32’
P512’
P2’
Bit3
P16
P256
P1
Bit2
P16’
P256’
P1’
Bit1
P8
P128
1
Bit0
P8’
P128’
1
ECC Evaluation Register for MLC (MLC_ECC0W)
0x80000940
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MLC_ECC0W[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC0W[15:0]
ECC Evaluation Register for MLC (MLC_ECC1W)
0x80000944
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
MLC_ECC1W[30:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC1W[15:0]
To evaluate ECC for MLC, write acquired ECC to these registers. The MLC_ECC0W is
LSB word and MLC_ECC1W is MSB. The order of writing should be LSB first and then
MSB. After writing to MLC_ECC1W, ECC module starts evaluation and its state can be
monitored by checking MLC_STAT field of ECC_CTRL register.
After finishing evaluation, user can determine whether ECC error occurred or not by
checking EC0 flag of ECC_CTRL register or checking MLC_ECC0R & MLC_ECC1R
registers.
ECC Output Register for MLC (MLC_ECC0R)
0x80000948
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MLC_ECC0R[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC0R[15:0]
ECC Output Register for MLC (MLC_ECC1R)
0x8000094C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
MLC_ECC1R[30:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC1R[15:0]
If there are ECC error, the EC0 flag of ECC_CTRL register is set to 1. By reading
MLC_ERR1R & MLC_ERR0R register and using appropriate algorithm, user can fix
maximum 3 symbols of error.
Preliminary
16-4