TCC76 Datasheet, PDF (203/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
MEMORY CONTROLLER
SMEM_0 Type Cycle (Bus width >= Data width, URDY=0)
nCS
XA
nOE
tSH
nWE
ADDR0
tPW
tHLD
tSH
DQ
DQ_R
ADDR1
tPW
DQ_W
tHLD
SMEM_0 Type Cycle (Bus width < Data width, URDY=1, RDY=0)
nCS
tPW + tWait =
tPW₁ + tPW₂ + tWait
tSH + tWait =
tSH₁ + tSH₂ + tWait
XA
nOE
READY
tPW₁
tSH
ADDR0
tPW₂
tWait
tHLD tSH1
ADDR1
tPW
tSH2
tWait
tHLD
DQ
DQ_RL
DQ_RH
SMEM_1 Type Cycle (Bus width >= Data width, URDY=0)
nCS
XA
nOE
tSH
nWE
ADDR0
tPW
ADDR1
tHLD
tSH
tHLD
tPW
DQM1
DQM0
DQ[15:8]
DQ₁
DQ[7:0]
DQ₀
Figure 15.3 Basic Timing Diagram for External Memories
In case of IDE type memories, there are two chip-enable signals for it. In the TCC76x, each
enable signal can be controlled by offset address space. ‘nCS0’ reflects that the offset address
range of 0 ~ 0x1F is accessed, ‘nCS1’ reflects that 0x20 ~ 0x3F is accessed. For larger address
than 0x3F, if bit5 of address value means which enable signal is activated. (0 to ‘nCS0’, 1 to
‘nCS1’)
Preliminary
15-11