TCC76 Datasheet, PDF (172/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
LCD CONTROLLER
14.4 STN LCD
The LCDC generates VSYNC, HSYNC, PXCLK, ACBIAS, and PXDATA signals for STN LCD
driver.
Figure 14.4 shows 1bpp, 2bpp, 4bpp, 8bpp, and 16bpp of PXDATA memory
organization. BR of LCTRL register indicates whether pixel data in frame memory is big-
endian for 1bpp, 2bpp, or 4bpp mode. Figure 14.5 shows RGB configuration for color
STN LCD.
The timing diagram for STN mode is shown in Figure 14.7. VSYNC and HSYNC pulse
are controlled by the configurations of the LPC field of LHTIME and FLC field of
LVTIME1 and LVTIME2. Each field is related to the LCD size and display mode.
In 1bpp, 2bpp, 4bpp:
LPC
In 8pp and 16bpp (RGB):
LPC
=(Horizontal display size / pixel data width) – 1
= {3 * Horizontal display size / (pixel data width) – 1}
Pixel data width is determined by PXDW of LCTRL register. In the case of STN LCD
mode, it must be 4 or 8-bit width.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1BPP p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16
2BPP p15 p14
p13 p12
p11 p10
p9
p8
4BPP
p7
p6
p5
p4
8BPP
p3
p2
16BPP
p1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1BPP p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
2BPP p7
p6
p5
p4
p3
p2
p1
p0
4BPP
p3
p2
p1
p0
8BPP
p1
p0
16BPP
p0
a) BR=0
Preliminary
14-4