TCC76 Datasheet, PDF (92/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
TIMER / COUNTER
Following figure illustrates the basic behavior of timer / counter.
CONT= 1, IEN =1 , PWM =0 , TCKSEL= 0, TREF=3
TCLK
TCK
TCNT
0
1
2
3
4
5
6
TEQU
TCO
TCO
TCO is inverted
nTREQ
CONT =0 , IEN= 1, PWM= 1, TCKSEL=0 , TREF=3 , TMREF= 1
TCLK
TCK
TCNT
0
1
2
3
0
1
2
TMEQU
TEQU
TCO
nTREQ
Figure 6.2 Timing diagram of timer/counter
Timer/Counter n Counting Register (TCNTn)
31 30 29 28 27 26 25 24 23 22
0
15 14 13 12 11 10 9 8 7 6
TCNTn[15:0]
0x80000204 + (0x10 * n)
21 20 19 18 17 16
TCNTn[19:16]
543210
TCNTn is increased by 1 at every pulse of selected clock source. TCNTn can be set to
any value by writing to this register. In case of timer 4 and timer 5, it has 20 bits,
otherwise it has 16 bits.
Timer/Counter n Counting Reference Register (TREFn) 0x80000208 + (0x10 * n)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
TREFn[19:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFn[15:0]
When TCNTn is reached at TREFn and the CON flag of TCFGn register is set to 1, the
TCNTn is cleared to 0 at the next pulse of selected clock source. According to the TCFGn
settings, various kinds of operations may be done. In case of timer 4 and timer 5, it has 20
bit, otherwise it has 16 bit.
Preliminary
6-4