TCC76 Datasheet, PDF (155/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MISCELLANEOUS PERIPHERALS
ADC Control Register A (ADCCONA)
0x80000A80
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
STB X
ASEL
*) This register has the same functionality as that of ADCCON register. Only the register address is different.
ADC Status Register (ADCSTATUS)
0x80000A84
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
WBVCNT
R
RBVCNT
Reserved
RSELV
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RBDATA
Bit
31
30:28
27
26:24
23:19
18:16
15:10
9:0
Name
Reserved
WBVCNT
Reserved
RBVCNT
Reserved
RSEL
Reserved
RBDATA
R/W
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
X
0
X
Description
Command Write Buffer Valid entry count. Up to 4 entries
with different ASEL values can be posted to command buffer.
Read Data Buffer Valid entry count. Up to 4 entries.
Input channel number for current read data. Valid only if RBCNT
is not zero.
Read Buffer Data.
ADC Configuration Register (ADCCFG)
31 30 29 28 27 26 25 24 23 22
Reserved
15 14 13 12 11 10 9 8 7 6
CLKDIV
DLYSTC
NEOC 0
0x80000A88
21 20 19 18 17 16
543210
FIFOTH IRQE R8 APD SM
Bit
15:12
11:8
7
6
5:4
3
2
1
0
Name
CLKDIV
DLYSTC
NEOC
Reserved
FIFOTH
IRQE
R8
APD
SM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0x2
0x4
0
0
0
0
0
0
0
Description
Clock Divisor Value. ADCLK is divided by ((CLKDIV + 1) * 2).
Delay from SEL to STC (Start of Conversion) in ADC core CLK
count. Whenever SEL value changes, delay is inserted.
For test purpose only. Must be written as “0”
FIFO Threshold for interrupt assertion. Interrupt will be asserted
only if FIFOTH < (# of Valid Entry).
Interrupt Enable.
When this bit is “1”, two LSBs are truncated. (shift right). Only
“ADCSTATUS” register is affected by this bit.
Auto Power Down Enable. This bit is effective only if SM bit
(described below) is “1”. After conversion cycle is done, the ADC
core is forced to power down mode.
Single Mode Enable. When disabled (0), ADC conversion cycle
is repeated forever with the input selected by ASEL bits. When
enabled (1), only one cycle is executed.
Preliminary
12-3