TCC76 Datasheet, PDF (69/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CPU
3.2.6 Coprocessor CP15
The ARM940T cached processor macrocell includes the ARM9TDMI microprocessor
core, instruction and data caches, a write-buffer, and a protection unit for defining the
attributes of regions of memory.
The ARM940T incorporates two coprocessors:
CP14 which allows software access to the debug communications channel
CP15 which allows configuration of the caches, protection unit, and other system
options such as clock operation.
The register map of CP15 is shown in the following table.
Table 3.1 CP15 Register Map
Register
Function
Access
0
1
2
3
4
5
6
7
8
9
10 – 14
15
NOTE:
ID code / Cache type
note
Control
Read / Write
Cacheable
note
Write buffer control
Read / Write
Reserved
-
Protection region access permissions note
Protection region base/size control note
Cache operations
Write only
Reserved
-
Cache lockdown
Read / Write
Reserved
-
Test
Not accessed in normal operation
Register of 0, 2, 5, and 6 each provide access to more than one register. The
register accessed depends on the value of the opcode_2 field. Refer to the
register descriptions for further information.
3.2.7 Protection Unit
The protection unit is used to partition memory and set individual protection attributes
for each partition. The instruction address space and the data address space can each be
divided up to 8 regions of variable size.
The protection unit is programmed via CP15 registers 1, 2, 3, 5 and 6.
Before the protection unit is enabled, at least one valid data and instruction region must
be programmed. If they are not programmed, the ARM940T can enter a state that is
recoverable only by reset. Setting bit 0 of the CP15 register 1 (the control register)
enables the protection unit.
When the protection unit is disabled, all instruction fetches are non-cacheable and all
data accesses are non-cacheable and non-bufferable.
Preliminary
3-3