TCC76 Datasheet, PDF (168/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
DMA CONTROLLER
SWP1 [9]
0
1
Channel1 SWAP Enable bit
Do not Swap Channel1 Data.
Swap Channel1 Data.
When this bit is set, data to be written to destination address will be swapped.
For example, the 32bit source data which consists of 4bytes {D3,D2,D1,D0} will be stored
{D0,D1,D2,D3} in destination address. The 16bit source data which consists of 2bytes {D1,D0}
will be stored {D0,D1} in destination address.
SWP0[8]
0
1
Channel0 SWAP Enable bit
Do not Swap Channel0 Data.
Swap Channel0 Data.
Except for channel difference, the function controlled by this bit is the same as its SWP1 bit.
PRI[4]
0
1
PRIORITY
CHANNEL0 is the Highest Priority in FIXed mode.
CHANNEL1 is the Highest Priority in FIXed mode.
FIX [0]
Fixed Priority Operation
0
Round-Robin (Cyclic) Mode.
1
Fixed Priority Mode.
In round-robin mode, Each channel is enabled one by one every one hop transferring.
In Fixed mode, according to PRI bit, the highest channel is serviced first and lower priority
channel is serviced after higher priority channel operation is finished. See Figure 13.4 for more
information.
IDLE
IDLE
1HOP
1HOP
CH1
CH1 END
1HOP
CH0
CH0 END
IDLE
< 2CHANNEL TRANSFER with Fixed Priority (channel 1 higher priority) >
CH0
1HOP
WAIT
CH1
1HOP
WAIT
CH0
1HOP
WAIT
CH1
1HOP
WAIT
CH0
1HOP
< 2CHANNEL TRANSFER with Round Robin Priority >
Figure 13.4 Enabled 2Channel Transfer.
The CHANNEL1 Registers are not described in detail in this data sheet.
The function of CHANNEL1 Registers are the same as CHANNEL0 Register except for channel difference and
assigned address.
Preliminary
13-8