TCC76 Datasheet, PDF (30/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
1.4.4 TCC766 Pin Description
Signal Name Shared Signal
SD_CKE
SD_CLK
SD_nCS
XA[21]
XA[20]
XA[19]
XA[18]
XA[17]
XA[16]
XA[15]
XA[14]
XA[13]
XA[12]
XA[11]
XA[10]
XA[9]
XA[8]
XA[7]
XA[6]
XA[5]
XA[4]
XA[3]
XA[2]
XA[1]
XA[0]
XD[15]
XD[14]
XD[13]
XD[12]
XD[11]
XD[10]
XD[9]
XD[8]
XD[7]
XD[6]
XD[5]
XD[4]
XD[3]
XD[2]
XD[1]
XD[0]
nCS[3]
nCS[2]
nCS[1]
nCS[0]
nWE
nOE
READY
FCSN
GPIO_B[0]
GPO
SD_nCLK / GPIO_B[1]
DQM[0]
DQM[1]
DQS[1]
DQS[0]
SD_nRAS
SD_nCAS
SD_BA[1]
SD_BA[0]
GPIO_B[5]
GPIO_B[4] / TESTCS2
GPIO_B[3]
GPIO_B[2] / TESTCS0
Ball
L9
P8
M8
L7
N7
L6
L5
P7
D5
N4
N2
N3
N5
M1
M5
M3
L2
L4
K3
J4
P14
J2
J3
J5
H4
H5
L3
F2
E1
E9
F3
D1
A2
B1
F5
C2
D3
G5
F10
H16
F11
M9
R7
R8
P6
N8
D12
K13
C14
Table 1.6 TCC766 Pin Description
Type Description – TCC766
External Memory Interface Pins
I/O SDRAM Clock Enable signal. Active high. / GPIO_B[0]
SDRAM Clock / GPO. SD_CLK can be used as a general
I/O purpose output. Refer to section “MEMORY CONTROLLER”.
(MCFG register Bit[3] and Bit[1])
I/O
Chip select signal for SDRAM, Active low / Inverted SD_CLK for
DDR SDRAM / GPIO_B[1]
I/O External Bus Address Bit [21] / Data I/O Mask 0
I/O External Bus Address Bit [20] / Data I/O Mask 1
I/O External Bus Address Bit [19] / DDR SDRAM Data Strobe [1]
I/O External Bus Address Bit [18] / DDR SDRAM Data Strobe [0]
I/O External Bus Address Bit [17]
I/O External Bus Address Bit [16] / SDRAM RAS signal
I/O External Bus Address Bit [15] / SDRAM CAS signal
I/O External Bus Address Bit [14] / SDRAM Bank Address 1
I/O External Bus Address Bit [13] / SDRAM Bank Address 0.
I/O External Bus Address Bit [12]
I/O External Bus Address Bit [11]
I/O External Bus Address Bit [10]
I/O External Bus Address Bit [9]
I/O External Bus Address Bit [8]
I/O External Bus Address Bit [7]
I/O External Bus Address Bit [6]
I/O External Bus Address Bit [5]
I/O External Bus Address Bit [4]
I/O External Bus Address Bit [3]
I/O External Bus Address Bit [2]
I/O External Bus Address Bit [1]
I/O External Bus Address Bit [0]
I/O External Bus Data Bit [15]
I/O External Bus Data Bit [14]
I/O External Bus Data Bit [13]
I/O External Bus Data Bit [12]
I/O External Bus Data Bit [11]
I/O External Bus Data Bit [10]
I/O External Bus Data Bit [9]
I/O External Bus Data Bit [8]
I/O External Bus Data Bit [7]
I/O External Bus Data Bit [6]
I/O External Bus Data Bit [5]
I/O External Bus Data Bit [4]
I/O External Bus Data Bit [3]
I/O External Bus Data Bit [2]
I/O External Bus Data Bit [1]
I/O External Bus Data Bit [0]
I/O
External Bus Chip Select 3 / GPIO_B[5]. This pin should
be connected to FCSN.
External Bus Chip Select 2 / GPIO_B[4]. This pin has an
I/O internal connection to the USB2.0 module. Do not use for
external components.
I/O External Bus Chip Select 1 / GPIO_B[3]
External Bus Chip Select 0 / GPIO_B[2]. This pin has an
I/O internal connection to the USB2.0 module. Do not use for
external components.
I/O Static Memory Write Enable signal. Active low.
I/O Static Memory Output Enable signal. Active low.
I Ready information from external device.
I NOR Flash Chip Select. Should be connected to nCS[3].
Preliminary
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