TCC76 Datasheet, PDF (38/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
INTRODUCTION
Signal Name
USBH_DN
UT_TX
UT_RX
Shared Signal
GPIO_B[29]
GPIO_B[8] / SD_nCS
GPIO_B[9]
BCLK
LRCK
MCLK
DAO
DAI
GPIO_B[21] / BM[0]
GPIO_B[22] / BM[1]
GPIO_B[23]
GPIO_B[24] / BM[2]
GPIO_B[25]
CBCLK
CLRCK
CDAI
GPIO_A[1]
GPIO_A[2]
GPIO_A[3]
EXINT[3]
EXINT[2]
EXINT[1]
EXINT[0]
GPIO_A[15]
GPIO_A[14] / FGPIO[14]
GPIO_A[13] / FGPIO[13]
GPIO_A[12] / FGPIO[12]
GPIO_A[15]
GPIO_A[14]
GPIO_A[13]
GPIO_A[12]
GPIO_A[11]
GPIO_A[10]
EXINT[3]
EXINT[2] / FGPIO[14]
EXINT[1] / FGPIO[13]
EXINT[0] / FGPIO[12]
SDI2 / FGPIO[11] / SCL
FRM2 / FGPIO[10] / SDA
GPIO_A[9] / BW[1] SCK2 / FGPIO[9] / SCL
GPIO_A[8] / BW[0] SDO2 / FGPIO[8] / SDA
GPIO_A[7]
GPIO_A[6]
GPIO_A[5]
GPIO_A[4]
GPIO_A[3]
GPIO_A[2]
GPIO_A[1]
GPIO_A[0]
GPIO_B[29]
GPIO_B[28]
GPIO_B[27]
GPIO_B[26]
GPIO_B[25]
SDI1 / FGPIO[7]
FRM1 / FGPIO[6]
SCK1 / FGPIO[5]
SDO1 / FGPIO[4]
SDI0 / CDAI / FGPIO[3]
FRM0 / CLRCK / FGPIO[2]
SCK0 / CBCLK / FGPIO[1]
SDO0 / FGPIO[0]
USBH_DN
USBH_DP
USB_DN
USB_DP
DAI
GPIO_B[24] / BM[2] DAO
GPIO_B[23]
MCLK
GPIO_B[22] / BM[1] LRCK
Ball
K9
L11
L10
M11
N12
M13
N14
N15
A7
A6
C7
E4
E3
D3
B3
E4
E3
D3
B3
E7
B1
D7
A1
D5
C5
C8
B7
C7
A6
A7
B6
K9
R8
M9
P8
N15
N14
M13
N12
Type Description – TCC767
I/O USB Host D- signal / GPIO_B[29]
I/O
UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip
Select
I/O UART or IrDA RX data / GPIO_B[9]
Audio Interface Pins
I/O I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0
I/O I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1
I/O I2S System Clock / GPIO_B[23]
I/O
I2S Digital Audio data Output / GPIO_B[24] / Boot Mode
Bit 2
I/O I2S Digital Audio data Input / GPIO_B[25]
CD DSP Interface Pins
I/O CD Data Bit Clock Input / GPIO_A[1]
I/O CD Data Word Clock Input / GPIO_A[2]
I/O CD Data Input / GPIO_A[3]
External Interrupt Pins
I/O External Interrupt Request [3] / GPIO_A[15]
I/O External Interrupt Request [2] / GPIO_A[14] / FGPIO[14]
I/O External Interrupt Request [1] / GPIO_A[13] / FGPIO[13]
I/O External Interrupt Request [0] / GPIO_A[12] / FGPIO[12]
General Purpose I/O Pins
I/O GPIO_A[15] / External Interrupt Request 3
I/O GPIO_A[14] / External Interrupt Request 2 / Fast GPIO bit 14
I/O GPIO_A[13] / External Interrupt Request 1 / Fast GPIO bit 13
I/O GPIO_A[12] / External Interrupt Request 0 / Fast GPIO bit 12
I/O GPIO_A[11] / GSIO2 Data In / Fast GPIO bit 11 / I2C Clock.
I/O GPIO_A[10] / GSIO2 FRM / Fast GPIO bit 10 / I2C Data Line.
GPIO_A[9] / Bus Width bit 1 / GSIO2 Clock / Fast GPIO bit 9 / I2C
I/O
Clock. The status of BW[1:0] is latched at the rising edge of
nRESET and used to determine external bus width. Refer to section
“MEMORY CONTROLLER” for BW[1:0] description.
GPIO_A[8] / Bus Width bit 0 / GSIO2 Data Out / Fast GPIO bits 8 /
I/O
I2C Data Line. The status of BW[1:0] is latched at the rising edge of
nRESET and used to determine external bus width. Refer to section
“MEMORY CONTROLLER” for BW[1:0] description.
I/O GPIO_A[7] / GSIO1 Data In / Fast GPIO bit 7
I/O GPIO_A[6] / GSIO1 FRM / Fast GPIO bit 6
I/O GPIO_A[5] / GSIO1 Clock / Fast GPIO bit 5
I/O GPIO_A[4] / GSIO1 Data Output / Fast GPIO bit 4
I/O GPIO_A[3] / GSIO0 Data In / CD Interface Data / Fast GPIO bit 3
I/O GPIO_A[2] / GSIO0 FRM / CD Interface LRCK / Fast GPIO bit 2
I/O GPIO_A[1] / GSIO0 Clock / CD Interface BCLK / Fast GPIO bit 1
I/O GPIO_A[0] / GSIO0 Data Out / FGPIO[0]
I/O GPIO_B[29] / USBH_DN
I/O GPIO_B[28] / USBH_DP
I/O GPIO_B[27] / USB_DN
I/O GPIO_B[26] / USB_DP
I/O GPIO_B[25] / I2S Interface Data In.
GPIO_B[24] / Boot Mode bit 2 / I2S Interface Data Out.
The status of BM[2:0] is latched at the rising edge of nRESET and
I/O used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
I/O GPIO_B[23] / I2S Interface Master Clock.
GPIO_B[22] / Boot Mode bit 1 / I2S Interface LRCK.
The status of BM[2:0] is latched at the rising edge of nRESET and
I/O used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
Preliminary
1-28