TCC76 Datasheet, PDF (115/259 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005
CLOCK GENERATOR
EACLK (External/ADC) Control Register (EACLKmode)
31 30 29 28 27 26 25 24 23 22 21
0
DIVAD
15 14 13 12 11 10 9 8 7 6 5
DIVX2
EX2_PHASE[13:0]
0x80000410
20 19 18 17 16
AD_PHASE[5:0]
43210
Bit Name
Type Default Description
31:24 Reserved
R
0 Reserved
23:22 DIVAD
R/W 0 ADCLK Divisor Clock Select
DIVAD f_DIVAD (Divisor Clock Source Selected)
0 XIN input
1 PLL output
2 XTIN input
3 PLLDIVCLK (PLL clock divider output)
21:16 AD_PHASE R/W 0 ADCLK Clock Frequency Select
DIVMODE[5] AD_PHASE f_ADCLK (ADCLK Frequency)
0
0
f_DIVAD
0
1 ~ 0x2000 f_DIVAD* AD_PHASE / 2¹⁴
0
> 0x2000 Undefined. Do not use.
1
X
f_DIVAD / (AD_PHASE + 1)
15:14 DIVX2
R/W 0 EX2CLK / I2C Divisor Clock Select
DIVX2 f_DIVX2 (Divisor Clock Source Selected)
0 XIN input
1 PLL output
2 XTIN input
3 PLLDIVCLK (PLL clock divider output)
13:0 EX2_PHASE R/W 0 EX2CLK / I2C Clock Frequency Select
DIVMODE[4] EX2_PHASE f_EX2CLK (EX2CLK Frequency)
0
0
f_DIVX2
0
1 ~ 0x2000 f_DIVX2 * EX2_PHASE / 2¹⁴
0
> 0x2000 Undefined. Do not use.
1
X
f_DIVX2 / (EX2_PHASE + 1)
ADCLK is also controlled by ADC bit of CKCTRL register that can enable or disable ADCLK. If this bit is set
to high, ADCLK is disabled and if it is low, ADCLK is enabled
EX2CLK is also controlled by EX2 bit of CKCTRL register that can enable or disable EX2CLK. If this bit is set
to high, EX2CLK is disabled and if it is low, EX2CLK is enabled.
External clock is a user-programmable clock that can be used for various purposes. By setting GPIO registers,
GPIO_A10, GPIO_A9 and GPIO_B28 pins can output this clock to user application board. Care must be taken
not to use too high frequency that the these pins cannot cope with this signals, or the pins show no clock signal
out.
EX2CLK is also a clock source for internal I2C core module. When it is used as an external clock, internal I2C
core may not function dependent on the clock frequency.
EX2CLK must be programmed to meet the following equation if I2C core is enabled.
f_EX2CLK ≤ f_HCLK / 4.0
Preliminary
8-9