SH7018 Datasheet, PDF (99/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 13 (IW21)
0
1
Bit 12 (IW20)
0
1
0
1
Description
No idle cycle after accessing CS2 space
Inserts one idle cycle after accessing CS2
space
Inserts two idle cycles after accessing CS2
space
Inserts three idle cycles after accessing CS2
space
(Initial value)
Bit 11 (IW11)
0
1
Bit 10 (IW10)
0
1
0
1
Description
No idle cycle after accessing CS1 space
Inserts one idle cycle after accessing CS1
space
Inserts two idle cycles after accessing CS1
space
Inserts three idle cycles after accessing CS1
space
(Initial value)
Bit 9 (IW01)
0
1
Bit 8 (IW00)
0
1
0
1
Description
No idle cycle after accessing CS0 space
Inserts one idle cycle after accessing CS0
space
Inserts two idle cycles after accessing CS0
space
Inserts three idle cycles after accessing CS0
space
(Initial value)
• Bits 7 to 4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The
continuous access idle specification makes insertions to clearly delineate the bus intervals by
once negating the CSn signal when doing consecutive accesses of the same CS space. When a
write immediately follows a read, the number of idle cycles inserted is the larger of the two
values specified by IW and CW. Refer to section 7.4, Waits between Access Cycles, for
details.
CW3 specifies the continuous access idles for the CS3 space; CW2 specifies the continuous
access idles for the CS2 space; CW1 specifies the continuous access idles for the CS1 space
and CW0 specifies the continuous access idles for the CS0 space.
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