SH7018 Datasheet, PDF (214/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.3.4 Timing of Setting the Overflow Flag (OVF)
In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and
an interval timer interrupt is simultaneously requested (figure 11.6).
CK
TCNT
H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 11.6 Timing of Setting the OVF
11.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
If the timer counter (TCNT) overflows in the watchdog timer mode, the WOVF bit of the reset
control/status register (RSTCSR) is set to 1. If the RSTE bit of RSTCSR is set to 1, an internal
reset for the entire chip is generated when TCNT overflows. Figure 11.7 shows the timing.
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 11.7 Timing of Setting the WOVF Bit
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