SH7018 Datasheet, PDF (269/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

not set to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be
sure to clear the error flag.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCR1, the SCI1 requests a receive-data-full interrupt (RxI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) in the SCR1 is also set to 1, the SCI1 requests a
receive-error interrupt (ERI).
Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure
12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. The
procedure is as follows (the steps correspond to the numbers in the flowchart):
1. SCI1 initialization: Set the TxD and RxD pins using the PFC.
2. SCI1 status check and transmit data write: Read the serial status register (SSR1), check that the
TDRE bit is 1, then write transmit data in the transmit data register (TDR1) and clear TDRE to
0. The TxI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1.
3. Receive error handling: If a receive error occurs, read the ORER bit in SSR1 to identify the
error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving
cannot resume if ORER remains set to 1.
4. SCI1 status check and receive data read: Read the serial status register (SSR1), check that
RDRF is set to 1, then read receive data from the receive data register (RDR1) and clear RDRF
to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR1, and clear
RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Before the MSB (bit
7) of the current frame is received, read the TDRE bit and check that it is safe to write (if it
reads 1); if so, write data in TDR1, then clear TDRE to 0.
Note: In switching from transmitting or receiving to simultaneous transmitting and receiving,
simultaneously clear the TE bit and RE bit to 0, then simultaneously set the TE bit and RE
bit to 1.
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