SH7018 Datasheet, PDF (108/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

7.4 Waits between Access Cycles
When a read from a slow device is completed, data buffers may not go off in time to prevent data
conflicts with the next access. If there is a data conflict during memory access, the problem can be
solved by inserting a wait in the access cycle.
To enable detection of bus cycle starts, waits can be inserted between access cycles during
continuous accesses of the same CS space by negating the CSn signal once.
7.4.1 Prevention of Data Bus Conflicts
For the two cases of write cycles after read cycles, and read cycles for a different area after read
cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of
the BCR2 is inserted. When idle cycles already exist between access cycles, only the number of
empty cycles remaining beyond the specified number of idle cycles is inserted.
Figure 7.7 shows an example of idles between cycles. In this example, 1 idle between CSn space
cycles has been specified, so when a CSm space write immediately follows a CSn space read
cycle, 1 idle cycle is inserted.
T₁
T₂
T_idle
T₁
T₂
CK
Address
CSn
CSm
RD
WRL
Data
CSn space read
Idle cycle
CSm space write
Figure 7.7 Idle Cycle Insertion Example
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