SH7018 Datasheet, PDF (224/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 6: RIE
0
1
Description
Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)
requests are disabled.
(Initial value)
RxI and ERI interrupt requests can be cleared by reading the RDRF flag
or error flag (FER, PER, or ORER) after it has been set to 1, then
clearing the flag to 0, or by clearing RIE to 0.
Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)
requests are enabled.
• Bit 5—Transmit Enable (TE): Enables or disables the SCI1 serial transmitter.
Bit 5: TE
0
1
Description
Transmitter disabled
(Initial value)
The transmit data register empty bit (TDRE) in the serial status register
(SSR1) is locked at 1.
Transmitter enabled
Serial transmission starts when the transmit data register empty (TDRE)
bit in the serial status register (SSR1) is cleared to 0 after writing of
transmit data into the TDR1. Select the transmit format in the SMR1
before setting TE to 1.
• Bit 4—Receive Enable (RE): Enables or disables the SCI1 serial receiver.
Bit 4: RE
0
1
Description
Receiver disabled
(Initial value)
Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER,
ORER). These flags retain their previous values.
Receiver enabled
Serial reception starts when a start bit is detected in the asynchronous
mode, or synchronous clock input is detected in the clock synchronous
mode. Select the receive format in the SMR1 before setting RE to 1.
• Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only if the multiprocessor mode bit (MP) in the serial mode register
(SMR1) is set to 1 during reception.
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