SH7018 Datasheet, PDF (76/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

6.1.2 Block Diagram
Figure 6.1 is a block diagram of the INTC.
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ6
IRQ7
Input
control
MTU
CMT
SCI1
A/D
WDT
TIM2
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
CPU
Priority
ranking
judg-
ment
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR
IPR
ISR
IPRA to IPRH
Module bus
Bus
interface
INTC
MTU: Multifunction timer pulse unit
CMT: Compare match timer
SCI1: Serial communication interface
A/D: A/D converter
WDT: Watchdog Timer
TIM2: 8-bit timer
ICR: Interrupt control register
ISR: IRQ ststus register
IPRA to IPRH: Interrupt priority level setting
registers A to H
SR: Status register
Figure 6.1 INTC Block Diagram
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