SH7018 Datasheet, PDF (252/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

In receiving, the SCI1 operates as follows:
1. The SCI1 monitors the communication line. When it detects a start bit (0), the SCI1
synchronizes internally and starts receiving.
2. Receive data is shifted into the RSR1 in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI1 makes the
following checks:
a. Parity check. The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in the SMR1.
b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit
is checked.
c. Status check. RDRF must be 0 so that receive data can be loaded from the RSR1 into the
RDR1.
If the data passes these checks, the SCI1 sets RDRF to 1 and stores the received data in the
RDR1. If one of the checks fails (receive error), the SCI1 operates as indicated in table 12.11.
Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF
bit is not set to 1, so be sure to clear the error flags.
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCR1, the SCI1 requests a receive-data-full interrupt (RxI). If one of the error flags (ORER,
PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also
set to 1, the SCI1 requests a receive-error interrupt (ERI).
Figure 12.8 shows an example of SCI1 receive operation in the asynchronous mode.
Table 12.11 Receive Error Conditions and SCI1 Operation
Receive Error
Overrun error
Framing error
Parity error
Abbreviation
ORER
FER
PER
Condition
Data Transfer
Receiving of next data ends while Receive data not loaded
RDRF is still set to 1 in SSR1
from RSR1 into RDR1
Stop bit is 0
Receive data loaded from
RSR1 into RDR1
Parity of receive data differs from Receive data loaded from
even/odd parity setting in SMR1 RSR1 into RDR1
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