SH7018 Datasheet, PDF (167/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Contention between TGR Read and Input Capture: If an input capture signal is issued in the
T₁ state of the TGR read cycle, the read data is that after input capture transfer (figure 8.42).
TGR read cycle
T₁
T₂
φ
Address
Read signal
Input capture
signal
TGR
TGR
address
X
M
Internal data
M
bus
Figure 8.42 TGR Read and Input Capture Contention
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