SH7018 Datasheet, PDF (208/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.2.2 Timer Control/Status Register (TCSR)
The timer control/status register (TCSR) is an 8-bit read/write register. (The TCSR differs from
other registers in that it is more difficult to write to. See section 11.2.4, Register Access, for
details.) Its functions include selecting the clock input source and mode of the timer counter
(TCNT).
Bits 7 to 5 are initialized to 000 by a power-on reset or in standby mode. Bits 2 to 0 are initialized
to 000 by a power-on reset, but retain their values in the standby mode.
Bit: 7
6
5
4
OVF WT/IT TME
—
Initial value: 0
0
0
1
R/W: R/(W) R/W R/W
R
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
R
R/W R/W R/W
• Bit 7—Overflow Flag (OVF): Indicates that the TCNT has overflowed from H'FF to H'00 in
the interval timer mode. It is not set in the watchdog timer mode.
Bit 7: OVF
0
1
Description
No overflow of TCNT in interval timer mode
Cleared by reading OVF, then writing 0 in OVF
TCNT overflow in the interval timer mode
(Initial value)
• Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer.
Bit 6: WT/IT
0
1
Description
Interval timer mode
(Initial value)
Watchdog timer mode: WDTOVF signal output externally when TCNT
overflows. (Section 11.2.3, Reset Control/Status Register (RSTCSR),
describes in detail what happens when TCNT overflows in the watchdog
timer mode.)
• Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME
0
1
Description
Timer disabled: TCNT is initialized to H'00 and count-up stops
(Initial value)
Timer enabled: TCNT starts counting.
• Bits 4 and 3—Reserved: These bits are always read as 1. The write value should always be 1.
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