SH7018 Datasheet, PDF (123/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Channel 0: TIOR0L
Bit: 7
6
5
4
3
2
1
0
—
IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Note: When the TGRC or TGRD registers are set for buffer operation, these settings become
ineffective and the operation is as a buffer register.
• Bit 7—Reserved. This bit is always read as 0. The write value should always be 0.
• Bits 6 to 4—I/O Control D2 to D0 (IOD2 to IOD0): These bits set the TGRD register function.
• Bits 3 to 0—I/O Control C3 to C0 (IOC3 to IOC0): These bits set the TGRC register function.
Channel 0 (TIOR0H Register):
Bit 6: Bit 5: Bit 4:
IOB2 IOB1 IOB0 Description
0
0
0
TGR0B is an output Output disabled
(Initial value)
1
compare register
Initial
Output 0 on compare-match
1
0
1
output
is 0
Output 1 on compare-match
Toggle output on compare-match
1
0
0
Output disabled
1
1
0
1
Initial
output
is 1
Output 0 on compare-match
Output 1 on compare-match
Toggle output on compare-match
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