SH7018 Datasheet, PDF (405/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

19.3.2 Control Signal Timing
Table 19.5 Control Signal Timing
Conditions: V_CC = 3.0 to 3.6 V, PV_CC = 5.0 ± 0.5 V, PV_CC ≥ V_CC, AV_CC = 3.0 to 3.6 V,
AV_CC ≥ V_CC, V_SS = AV_SS = 0 V, f = 20 MHz, T_a = –20 to +75°C
Item
Symbol Min Max Unit Figure
RES rise and fall
RES pulse width
NMI rise and fall
RES setup time*
NMI setup time*
IRQ7, IRQ6, and IRQ3 to IRQ0 setup time*
(edge detection)
t , _RESr
t _RESf
t _RESW
t , _NMIr
t _NMIf
t _RESS
t _NMIS
t _IRQES
—
200 ns
Figure 19.4
40
—
t _cyc
—
200 ns
35
—
ns
Figure 19.4,
35
—
ns
Figure 19.5
35
—
ns
IRQ7, IRQ6, and IRQ3 to IRQ0 setup time*
(level detection)
t _IRQLS
35
—
ns
NMI hold time
t _NMIH
35
—
ns
Figure 19.5
IRQ7, IRQ6, and IRQ3 to IRQ0 hold time
t _IRQEH
35
—
ns
Note: * The RES, NMI, IRQ7, IRQ6, and IRQ3 to IRQ0 signals are input asynchronously. If the
setup time indicated is maintained, the clock rise (in the case of RES) or fall (in the case of
NMI, IRQ7, IRQ6, and IRQ3 to IRQ0) will be recognized as a change in level. If the setup
time indicated is not maintained, the change may not be recognized until the next clock rise
or fall.
CK
RES
t_RESf
t_RESS
V_IH
V_IL
t_RESW
t_RESr
t_RESS
V_IH
V_IL
Figure 19.4 Reset Input Timing
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