SH7018 Datasheet, PDF (186/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.1.2 Block Diagram
Figure 9.1 shows a block diagram of 8-bit timer 2 (TIM2).
CMI
(interrupt
request
signal)
Interrupt
control
Clock
Clock
selection
φ/2
φ/8
φ/32
φ/128
φ/512
φ/2048
φ/4096
T2COR
Comparator
T2CNT
T2CSR
Module bus
Bus
interface
8-bit timer 2
T2CSR: Timer 2 control/status register
T2CNT: Timer 2 counter
T2COR: Timer 2 constant register
Figure 9.1 Block Diagram of 8-Bit Timer 2
9.1.3 Register Configuration
8-bit timer 2 (TIM2) has three registers for compare match cycle setting, clock selection, and other
functions. The register configuration is shown in table 9.1.
All the registers are 16 bits in size, and are initialized by a power-on reset.
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