SH7018 Datasheet, PDF (288/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

13.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample and hold circuit. The A/D converter samples the analog
input at time t_D after the ADST bit is set to 1 in the A/D control/status register (ADCSR), then
starts conversion. Figure 13.5 shows the A/D conversion timing, and table 13.4 shows A/D
conversion times.
As shown in figure 13.5, A/D conversion time tCONV consists of A/D conversion start delay time
t_D and analog input sampling time t_SPL. The length of tD is not fixed, but is determined by the
timing of the write to ADSCR. The total conversion time therefore varies within the ranges shown
in table 13.4.
In scan mode, the t_CONV values given in table 13.4 apply to the first conversion. In the second and
subsequent conversions, t_CONV is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
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