SH7018 Datasheet, PDF (13/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

14.3 Register Descriptions......................................................................................................... 283
14.3.1 Port A IO Register L (PAIORL) .......................................................................... 283
14.3.2 Port A Control Registers L1 and L2 (PACRL1, PACRL2) ................................. 283
14.3.3 Port B IO Register (PBIOR)................................................................................. 288
14.3.4 Port B Control Registers 1 and 2 (PVCR1, PBCR2)............................................ 288
14.3.5 Port C IO Register (PCIOR)................................................................................. 291
14.3.6 Port C Control Register (PCCR) .......................................................................... 292
14.3.7 Port D IO Register L (PDIORL) .......................................................................... 295
14.3.8 Port D Control Register L (PDCRL).................................................................... 296
14.3.9 Port E IO Register (PEIOR) ................................................................................. 298
14.3.10 Port E Control Register 2 (PECR2)...................................................................... 299
Section 15 I/O Ports (I/O).................................................................................................. 301
15.1 Overview............................................................................................................................ 301
15.2 Port A................................................................................................................................. 301
15.2.1 Register Configuration ......................................................................................... 302
15.2.2 Port A Data Register L (PADRL) ........................................................................ 303
15.3 Port B ................................................................................................................................. 304
15.3.1 Register Configuration ......................................................................................... 304
15.3.2 Port B Data Register (PBDR)............................................................................... 305
15.4 Port C ................................................................................................................................. 306
15.4.1 Register Configuration ......................................................................................... 306
15.4.2 Port C Data Register (PCDR)............................................................................... 307
15.5 Port D................................................................................................................................. 308
15.5.1 Register Configuration ......................................................................................... 308
15.5.2 Port D Data Register L (PDDRL) ........................................................................ 309
15.6 Port E ................................................................................................................................. 310
15.6.1 Register Configuration ......................................................................................... 310
15.6.2 Port E Data Register (PEDR) ............................................................................... 311
15.7 Port F ................................................................................................................................. 312
15.7.1 Register Configuration ......................................................................................... 312
15.7.2 Port E Data Register (PFDR) ............................................................................... 313
Section 16 160 kB Flash Memory (F-ZTAT).............................................................. 315
16.1 Features.............................................................................................................................. 315
16.2 Overview............................................................................................................................ 316
16.2.1 Block Diagram...................................................................................................... 316
16.2.2 Mode Transitions.................................................................................................. 317
16.2.3 On-Board Programming Modes ........................................................................... 318
16.2.4 Flash Memory Emulation in RAM....................................................................... 320
16.2.5 Differences between Boot Mode and User Program Mode ................................. 321
16.2.6 Block Configuration ............................................................................................. 322
16.3 Pin Configuration .............................................................................................................. 322
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