SH7018 Datasheet, PDF (392/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 18.1 Power-Down State Conditions
State
Entering
Mode Procedure
On-Chip
Peripheral CPU
Clock CPU Modules Registers RAM
Sleep Execute SLEEP Run Halt Run
instruction with
SBY bit set to 0
in SBYCR
Held
Held
I/O
Ports
Held
Canceling
Procedure
• Interrupt
• DMAC
address error
• Power-on
reset
Stand- Execute SLEEP Halt Halt Halt*¹
by instruction with
SBY bit set to 1
in SBYCR
Held
Held
Held or •
high
impe-
•
dance*²
NMI interrupt
Power-on
reset
SBYCR: standby control register.
SBY: standby bit
Notes: 1. Some bits within on-chip peripheral module registers are initialized by the standby
mode; some are not. Refer to table 18.3, Register States in the Standby Mode, in
section 18.4.1, Transition to Standby Mode. Also refer to the register descriptions for
each peripheral module.
2. The status of the I/O port in standby mode is set by the port high impedance bit (HIZ) of
the SBYCR. Refer to section 18.2, Standby Control Register (SBYCR). For pin status
other than for the I/O port, refer to Appendix B, Pin Status.
18.1.2 Related Register
Table 18.2 shows the register used for power-down state control.
Table 18.2 Related Register
Name
Abbreviation R/W Initial Value Address
Access Size
Standby control register SBYCR
R/W H'1F
H'FFFF8614 8, 16, 32
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