SH7018 Datasheet, PDF (158/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.6 Operation Timing
8.6.1 Input/Output Timing
TCNT Count Timing: Count timing for the TCNT counter with internal clock operation is shown
in figure 8.28.
φ
Internal
clock
Falling edge
Rising edge
Falling edge
TCNT
input
clock
TCNT
N–1
N
N+1
N+2
Figure 8.28 TCNT Count Timing during Internal Clock Operation
Output Compare Output Timing: The compare-match signal is generated at the final state of
TCNT and TGR matching. When a compare-match signal is issued, the output value set in TIOR
or TOCR is output to the output compare output pin (TIOC pin). After TCNT and TGR matching,
a compare-match signal is not issued until immediately before the TCNT input clock.
Output compare output timing (normal mode and PWM mode) is shown in figure 8.29.
142