SH7018 Datasheet, PDF (311/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 0—PC0 Mode (PC0MD): Selects the function of the PC0/A0 pin.
Bit 0: PC0MD
0
1
Description
General input/output (PC0)
Address output (A0)
(Initial value)
14.3.7 Port D IO Register L (PDIORL)
Port D IO register L (PDIORL) is a 16-bit readable/writable register that selects the input/output
direction of the pins in port D. The bits of this register correspond to the various pins. PDIORL is
enabled when the port D pins function as general input/output (PD7 to PD0), and disabled
otherwise.
When the port D pins function as PD7 to PD0, a pin becomes an output when the corresponding
bit in PDIORL is set to 1, and an input when the bit is cleared to 0.
PDIORL is initialized to H'0000 by an external power-on reset. However, it is not initialized by a
WDT reset, in standby mode, or in sleep mode. In these cases it retains its previous data.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
PD7IOR PD6IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR PD0IOR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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