SH7018 Datasheet, PDF (210/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 7: WOVF
0
1
Description
No TCNT overflow in watchdog timer mode
(Initial value)
Cleared when software reads WOVF, then writes 0 in WOVF
Set by TCNT overflow in watchdog timer mode
• Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if the TCNT
overflows in the watchdog timer mode.
Bit 6: RSTE
0
1
Description
Not reset when TCNT overflows
(Initial value)
LSI not reset internally, but TCNT and TCSR reset within WDT.
Reset when TCNT overflows
• Bit 5—Reserved: This bit is always read as 0. The write value should always be 0.
• Bits 4 to 0—Reserved: These bits are always read as 1. The write value should always be 1.
11.2.4 Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they
are more difficult to write to. The procedures for writing and reading these registers are given
below.
Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions.
The TCNT and TCSR both have the same write address. The write data must be contained in the
lower byte of the written word. The upper byte must be H'5A (for the TCNT) or H'A5 (for the
TCSR) (figure 11.2). This transfers the write data from the lower byte to the TCNT or TCSR.
Writing to the TCNT
15
Address: H'FFFF8610
H'5A
87
0
Write data
Writing to the TCSR
15
Address: H'FFFF8610
H'A5
87
0
Write data
Figure 11.2 Writing to the TCNT and TCSR
194