SH7018 Datasheet, PDF (137/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit n: SYNCn
Description
0
Timer counter (TCNTn) independent operation
(Initial value)
(TCNTn preset/clear unrelated to other channels)
1
Timer counter synchronous operation*¹
TCNTn synchronous preset/ synchronous clear*² possible
Note:
1. Minimum of two channel SYNC bits must be set to 1 for synchronous operation.
2. TCNT counter clear sources (CCLR2 to CCLR0 bits of the TCR register) must be set in
addition to the SYNC bit in order to have clear synchronization.
n = 2 to 0.
8.3 Bus Master Interface
8.3.1 16-Bit Registers
The timer counters (TCNT) and general registers (TGR) are 16-bit registers. A 16-bit data bus to
the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit
units. Figure 8.2 shows an example of 16-bit register access operation.
Internal data bus
Upper 8 bits
Module data bus
Bus master
Bus
interface
Lower 8 bits
TCNTH
TCNTL
Figure 8.2 16-Bit Register Access Operation (Bus Master ↔ TCNT (16 Bits))
8.3.2 8-Bit Registers
All registers other than the TCNT and general registers (TGR) are 8-bit registers. These are
connected to the CPU by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both
possible (figure 8.3 to figure 8.5).
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