SH7018 Datasheet, PDF (229/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the TDR1 did not contain valid data, so transmission has ended. TEND is a read-
only bit and cannot be written.
Bit 2: TEND
0
1
Description
Transmission is in progress
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE.
End of transmission
(Initial value)
TEND is set to 1 when the chip is power-on reset or in standby mode, TE is
cleared to 0 in the serial control register (SCR1), or TDRE is 1 when the last bit
of a one-byte serial character is transmitted.
• Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is selected for receiving. The MPB is a read-only bit and cannot
be written.
Bit 1: MPB
0
1
Description
Multiprocessor bit value in receive data is 0
(Initial value)
If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains
its previous value.
Multiprocessor bit value in receive data is 1
• Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added
to transmit data when a multiprocessor format is selected for transmitting. The setting of the
MPBT bit is ignored in the clock synchronous mode, when the multiprocessor format is not
being used, and when transmission is not taking place.
Bit 0: MPBT
0
1
Description
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
(Initial value)
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