SH7018 Datasheet, PDF (82/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

6.3 Description of Registers
6.3.1 Interrupt Priority Registers A to H (IPRA to IPRH)
Interrupt priority registers A to H (IPRA to IPRH) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRA to IPRH bits is shown in
table 6.4.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 6.4 Interrupt Request Sources and IPRA to IPRH
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
15 to 12
IRQ0
Reserved
Reserved
MTU0
MTU2
Reserved
A/D
WDT, TIM2
Bits
11 to 8
7 to 4
IRQ1
IRQ2
Reserved IRQ6
Reserved Reserved
MTU0
MTU1
MTTU2
Reserved
Reserved Reserved
Reserved CMT0
Reserved Reserved
3 to 0
IRQ3
IRQ7
Reserved
MTU1
Reserved
SCI1
CMT1
Reserved
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to
each register. Each of the corresponding interrupt priority ranks are established by setting a value
from H'0 (0000) to H'F (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0.
Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting
H'F. 8-bit timers 1 and 2 are set to the same priority rank.
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